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Spartan-6 FPGA Implementation of AES Algorithm

机译：斯巴达-6 AES算法的FPGA实现

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摘要

Due to advancement of Information and Technology, Artificial Intelligence and Internet of things, Space Technology and E-Commerce world that changes the life of human being as because of that it is possible to interact with people by electronic means to everybody, every time, everywhere. It is possible to have seamless fabric of electronic connection with the help of electronic devices. The data which transmitted ceaselessly through electronic media which provides more assurance on cryptography to secure the data and communication. AES algorithm design is Implemented in VHDL and Simulated and Synthesized in Integrated Environment synthesis Xilinx 14.2 version software, then after actual result of AES Operation is validated on hardware in the form of Spartan 6 FPGA. From the work completed in this paper it is observed that AES Algorithm which designed and Implemented with less FPGA Hardware, Less Power consumption and Better Throughput of the Cryptosystem. Hence AES Algorithm which implemented on Spartan-6 FPGA can Give the possibility of portability, applications Compatibility and Improvement of security levels.
机译：由于信息和技术的推进，人工智能和事物互联网，空间技术和电子商务世界改变了人类的生命，因为有可能通过电子手段与人们互动，每次都在各处。可以在电子设备的帮助下具有无缝的电子连接结构。通过电子媒体不断传输的数据，该媒体在加密中提供更多保证，以确保数据和通信。 AES算法设计是在VHDL中实现的，并在集成环境综合Xilinx 14.2版本软件中模拟和合成，然后在斯巴达6 FPGA的形式验证AES操作的实际结果之后。从本文完成的工作开始，AES算法以较少的FPGA硬件设计和实现，较少的功耗和更好的密码系统吞吐量。因此，在Spartan-6 FPGA上实现的AES算法可以提供便携性的可能性，应用程序兼容性和安全级别的提高。

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