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首页> 外文会议>Metrology, Inspection, and Process Control for Microlithography XX pt.2 >Critical Dimension Variations of I-Line Processes due to Swing Effects
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Critical Dimension Variations of I-Line Processes due to Swing Effects

机译：由于摆动效应，I线工艺的关键尺寸变化

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As chip dimensions decrease, I-line processes remain of interest for most uncritical layers: they provide the needed performance at a low cost and high throughput. However the critical dimensions (CD) and overlay requirements for the newest technologies are much tighter than they used to be, reducing significantly the process windows. Sources of variations of CD range and CD mean should be well known and the process window set up so as to minimize the sensitivity to small variations. For lower resist thickness, although using partially dyed I-line resist, one may have to deal with huge swing effects. Resist thickness and stack variations are then the main contributors to the high CD distribution This article focuses on CD instabilities caused by resist thickness fluctuations in the case where a stack layer is subject to variations. The influence of resist thickness variations is first considered, pointing out the importance of thickness control methods. The real resist thickness repartition on stacked wafers depends not only on global coating uniformity but also on local topography. Some examples of resist repartition and its impact on CD-uniformity are provided. The added contributions of resist and stack to a global swing effect are then discussed on the basis of experimental data. Significant differences of swing behavior are experimentally observed between critical chip structures and the usually monitored PCI kerf structure. A simulation illustrates the effect of the local stack thickness and resist thickness and to better understand those differences, together with cross section thickness measurements. The choice of an appropriate CD control structure is finally dealt with.
机译：随着芯片尺寸的减小，大多数非关键层仍需要关注I线工艺：它们以低成本和高吞吐量提供了所需的性能。但是，最新技术的关键尺寸（CD）和覆盖要求比以前严格得多，从而大大减少了工艺窗口。 CD范围和CD均值的变化源应该是众所周知的，并设置处理窗口，以使对小变化的敏感性最小。对于较低的抗蚀剂厚度，尽管使用部分染色的I线抗蚀剂，可能必须应对巨大的摆动效应。然后，抗蚀剂的厚度和叠层变化是导致高CD分布的主要因素。本文重点讨论在叠层发生变化的情况下，由抗蚀剂厚度波动引起的CD不稳定性。首先考虑抗蚀剂厚度变化的影响，指出厚度控制方法的重要性。堆叠晶圆上实际抗蚀剂厚度的重新分配不仅取决于总体涂层均匀性，还取决于局部形貌。提供了一些抗蚀剂重新分配及其对CD均匀性的影响的示例。然后根据实验数据讨论了抗蚀剂和叠层对整体摆动效应的附加贡献。实验上观察到了关键芯片结构和通常监视的PCI切口结构之间的摆动行为的显着差异。仿真说明了局部叠层厚度和抗蚀剂厚度的影响，并更好地了解了这些差异以及横截面厚度的测量结果。最终要解决适当CD控制结构的选择。

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