• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>Novel Materials and Processes for Advanced CMOS >The Influence of Defects on Compatibility and Yield of the HfO_2-PolySilicon Gate Stack for CMOS Integration
【24h】

The Influence of Defects on Compatibility and Yield of the HfO_2-PolySilicon Gate Stack for CMOS Integration

机译：缺陷对用于CMOS集成的HfO_2-多晶硅栅堆叠的兼容性和良率的影响

获取原文
获取原文并翻译 | 示例
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Hafnium-based dielectrics are under wide consideration for high-K gate dielectric applications. Since the gate electrode typically used in CMOS integration consists of polysilicon with n- or p-type dopants, compatibility of the HfD_2 layer with the polySi deposition and dopant activation steps is critical. Capacitors were fabricated with HfO_2 films deposited by ALD and MOCVD, and using polysilicon gate electrodes deposited by CVD processes. These devices showed leakage failures with yields that were observed to depend on the area, dielectric thickness and annealing conditions during the process. Investigation of the root cause of these leakage failures suggested that the leakage failures may be caused by a defect-related mechanism. The implication of this is that the leakage occurs at localized 'defect' sites rather than broadly through the HfO_2 layer. Emission microscopy analysis and physical characterization of the HfO_2 film were used to corroborate the proposed model. Defect density was observed to be strongly dependent on the processing of the dielectric film. In order to make Hf-based dielectric stacks compatible with polysilicon for conventional CMOS transistor integration with acceptable yield, further post-deposition treatment may be necessary to eliminate or cure the defects.
机译：high基电介质在高K栅极电介质应用中得到了广泛的考虑。由于通常用于CMOS集成的栅电极由具有n型或p型掺杂剂的多晶硅组成，因此HfD_2层与多晶硅沉积和掺杂剂激活步骤的相容性至关重要。使用通过ALD和MOCVD沉积的HfO_2膜，以及通过CVD工艺沉积的多晶硅栅电极制造电容器。这些器件显示出泄漏故障，其成品率取决于该过程中的面积，电介质厚度和退火条件。对这些泄漏故障的根​​本原因的研究表明，泄漏故障可能是由与缺陷相关的机制引起的。这意味着泄漏发生在局部“缺陷”部位，而不是广泛地通过HfO_2层。 HfO_2薄膜的发射显微镜分析和物理表征被用于证实所提出的模型。观察到缺陷密度强烈依赖于介电膜的加工。为了使Hf基介电堆栈与多晶硅兼容，并具有可接受的良率，可用于常规CMOS晶体管集成，可能需要进一步的后沉积处理以消除或固化缺陷。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号