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Characterization, integration and reliability of HfO$_2$ and LaLuO$_3$ high-κ/metal gate stacks for CMOS applications

机译:用于CMOS应用的HfO $ _2 $和LaLuO $ _3 $高κ/金属栅叠层的特性,集成和可靠性

摘要

The continued downscaling of MOSFET dimensions requires an equivalent oxide thickness (EOT) of the gate stack below 1 nm. An EOT below 1.4 nm is hereby enabled by the use of high-kappa/metal gate stacks. LaLuO3 and HfO2 are investigated as two different high-kappa oxides on silicon in conjunction with TiN as the metal electrode. LaLuO3 and its temperature-dependent silicate formation are characterized by hard X-ray photoemission spectroscopy (HAXPES). The effective attenuation length of LaLuO3 is determined between 7 and 13 keV to enable future interface and diffusion studies. In a first investigation of LaLuO3 on germanium, germanate formation is shown. LaLuO3 is further integrated in a high-temperature MOSFET process flow with varying thermal treatment. The devices feature drive currents up to 70µA/µm at 1µm gate length. Several optimization steps are presented. The effective device mobility is related to silicate formation and thermal budget. At high temperature the silicate formation leads to mobility degradation due to La-rich silicate formation. The integration of LaLuO3 in high-T processes delicately connects with the optimization of the TiN metal electrode. Hereby, stoichiometric TiN yields the best results in terms of thermal stability with respect to Si-capping and high-kappa oxide. Different approaches are presented for a further EOT reduction with LaLuO3 and HfO2. Thereby the thermodynamic and kinetic predictions are employed to estimate the behavior on the nanoscale. Based on thermodynamics, excess oxygen in the gate stack, especially in oxidized metal electrodes, is identified to prevent EOT scaling below 1.2 nm. The equivalent oxide thickness of HfO2 gate stacks is scalable below 1 nm by the use of thinned interfacial SiO2. The prevention of oxygen incorporation into the metal electrode by Si-capping maintains the EOT after high temperature annealing. Redox systems are employed within the gate electrode to decrease the EOT of HfO2 gate stacks. A lower limit found was EOT=5 Å for Al doping inside TiN. The doping of TiN on LaLuO3 is proven by electron energy loss spectroscopy (EELS) studies to modify the interfacial silicate layer to La-rich silicates or even reduce the layer. The oxide quality in Si/HfO2/TiN gate stacks is characterized by charge pumping and carrier mobility measurements on 3d MOSFETs a.k.a. FinFETs. The oxide quality in terms of the number of interface (and oxide) traps on top- and sidewall of FinFETs is compared for three different annealing processes. A high temperature anneal of HfO2 improves significantly the oxide quality and mobility. The gate oxide integrity (GOI) of gate stacks below 1 nm EOT is determined by time-dependent dielectric breakdown (TDDB) measurements on FinFETs with HfO2/TiN gate stacks. A successful EOT scaling has always to consider the oxide quality and resulting reliability. Degraded oxide quality leads to mobility degradation and earlier soft-breakdown, i.e. leakage current increase.
机译:MOSFET尺寸的持续缩小要求栅极叠层的等效氧化物厚度(EOT)低于1 nm。通过使用高κ/金属栅叠层,可以实现低于1.4 nm的EOT。研究了LaLuO3和HfO2作为硅上的两种不同的高k氧化物,结合TiN作为金属电极。 LaLuO3及其随温度变化的硅酸盐形成的特征在于硬X射线光发射光谱(HAXPES)。 LaLuO3的有效衰减长度确定在7到13 keV之间,以便将来进行界面和扩散研究。在对LaLuO3的锗的首次研究中,显示了锗酸盐的形成。 LaLuO3进一步集成到具有不同热处理的高温MOSFET工艺流程中。该器件在1µm栅极长度下的驱动电流高达70µA / µm。介绍了几个优化步骤。有效的器件迁移率与硅酸盐的形成和热收支有关。在高温下,由于富含镧的硅酸盐的形成,硅酸盐的形成导致迁移率降低。 LaLuO3在高T工艺中的集成与TiN金属电极的优化紧密相连。因此,就硅覆盖和高κ氧化物而言,化学计量的TiN产生了最佳的热稳定性。提出了不同的方法来进一步减少LaLuO3和HfO2的EOT。因此,采用热力学和动力学预测来估计纳米级的行为。根据热力学,可以确定栅堆叠中的多余氧气,尤其是氧化金属电极中的多余氧气,可以防止EOT尺寸降至1.2 nm以下。 HfO2栅叠层的等效氧化物厚度可通过使用更薄的界面SiO2扩展到1 nm以下。通过硅封盖防止氧气掺入金属电极中,可以在高温退火后保持EOT。在栅电极内采用氧化还原系统以降低HfO2栅堆叠的EOT。对于TiN内部的Al掺杂,发现的下限为EOT = 5Å。通过电子能量损失谱(EELS)研究证明将TiN掺杂在LaLuO3上可以将界面硅酸盐层改性为富含La的硅酸盐,甚至还原该层。 Si / HfO2 / TiN栅叠层中的氧化物质量的特征是在3d MOSFETs又称为FinFETs上进行电荷泵和载流子迁移率测量。针对三种不同的退火工艺,比较了FinFET顶部和侧壁上的界面(和氧化物)陷阱的氧化物质量。 HfO2的高温退火可显着改善氧化物质量和迁移率。低于1 nm EOT的栅极堆叠的栅极氧化物完整性(GOI)由具有HfO2 / TiN栅极堆叠的FinFET上随时间变化的介电击穿(TDDB)测量确定。成功的EOT缩放必须始终考虑氧化物的质量和可靠性。氧化物质量下降导致迁移率降低和较早的软击穿,即漏电流增加。

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  • 作者

    Nichau Alexander;

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  • 年度 2013
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  • 原文格式 PDF
  • 正文语种 eng
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