• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>Optical Microlithography XI >Practical approach to control the full-chip-level gate CD in DUVlithography,
【24h】

Practical approach to control the full-chip-level gate CD in DUVlithography,

机译：在DUVlithography中控制全芯片级栅极CD的实用方法，

获取原文
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Abstract: A practical method to control the full chip level gate CD of a logic device with a 0.28 micrometer minimum design rule in DUV lithography is evaluated using an automatic optical proximity correction (OPC) software with empirical modeling. The CD variation on a chip results from the proximity and uniformity CD errors. The proximity error occupying more than 40% of total CD variation is caused by the pattern geometry, resist process, and mask CD error. In this paper, the OPC has been applied to line width narrowing and line-end shortening. The line-end shortening has been corrected by only the line- end extension instead of adding serifs which can be mistaken for defects during mask inspection. From this work, 43% reduction of the CD variation induced by proximity in the 3$sigma standard deviation has been achieved at the 14 nm correction unit. Furthermore, the focus margin of 1.2 micrometer after OPC has been guaranteed. The results of line- end correction show that the line-end extension correction is sufficient to correct the overlap mismatching between the active and gate layers. !13
机译：摘要：使用具有经验建模的自动光学邻近校正（OPC）软件，评估了一种控制DUV光刻中具有0.28微米最小设计规则的逻辑器件的全芯片级门CD的实用方法。芯片上CD的变化是由接近度和均匀性CD误差引起的。接近误差占总CD变化的40％以上是由图案几何形状，抗蚀剂工艺和掩模CD误差引起的。在本文中，OPC已应用于线宽变窄和线端缩短。线端缩短仅通过线端扩展得到纠正，而不是添加在衬板检查期间可能被误认为是缺陷的衬线。通过这项工作，在14 nm校正单元处，由于3σ标准差的接近而导致的CD变化减少了43％。此外，在OPC之后的焦距保证为1.2微米。线端校正的结果表明，线端延伸校正足以校正有源层和栅极层之间的重叠失配。 ！13

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号