• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>Optical Microlithography XI >Practical approach to control the full-chip-level gate CD in DUV lithography
【24h】

Practical approach to control the full-chip-level gate CD in DUV lithography

机译：在DUV光刻中控制全芯片级栅极CD的实用方法

获取原文
获取原文并翻译 | 示例
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Abstract: A practical method to control the full chip level gateCD of a logic device with a 0.28 micrometer minimumdesign rule in DUV lithography is evaluated using anautomatic optical proximity correction (OPC) softwarewith empirical modeling. The CD variation on a chipresults from the proximity and uniformity CD errors.The proximity error occupying more than 40% of total CDvariation is caused by the pattern geometry, resistprocess, and mask CD error. In this paper, the OPC hasbeen applied to line width narrowing and line-endshortening. The line-end shortening has been correctedby only the line- end extension instead of addingserifs which can be mistaken for defects during maskinspection. From this work, 43% reduction of the CDvariation induced by proximity in the 3$sigma standarddeviation has been achieved at the 14 nm correctionunit. Furthermore, the focus margin of 1.2 micrometerafter OPC has been guaranteed. The results of line- endcorrection show that the line-end extension correctionis sufficient to correct the overlap mismatchingbetween the active and gate layers. !13
机译：摘要：使用具有经验模型的自动光学邻近校正（OPC）软件，评估了一种在DUV光刻中控制最小设计规则为0.28微米的逻辑器件的全芯片级gateCD的实用方法。芯片上的CD偏差是由接近度和均匀度CD误差引起的。接近度误差占总CD偏差的40％以上是由图案几何形状，抗蚀剂工艺和掩膜CD误差引起的。在本文中，OPC已应用于线宽变窄和线端变短。线端缩短仅通过线端扩展进行了校正，而不是添加了可能在掩膜检查期间被误认为是缺陷的分离线。通过这项工作，在14 nm校正单元上，通过3σ标准偏差接近引起的CD变异降低了43％。此外，在确保OPC之后，焦距为1.2微米。线端校正的结果表明，线端延伸校正足以校正有源层和栅极层之间的重叠失配。 ！13

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号