• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>Physics and technology of high-k materials 9 >Impact of Constant Voltage Stress on High-K Gate Dielectric for RF IC Performance
【24h】

Impact of Constant Voltage Stress on High-K Gate Dielectric for RF IC Performance

机译：恒定电压应力对高K栅极电介质对RF IC性能的影响

获取原文
获取原文并翻译 | 示例
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Challenges in modern CMOS RF IC design include optimizing gain, noise and linearity. These parameters are highly dependent on transconductance (g_m) and threshold voltage (V_t). Introduction of high-K dielectrics with metal gates in advanced CMOS gate stacks requires that the impact of any variation of g_m and V_t due to stress on RFIC performance needs to be investigated thoroughly. This paper investigates the effect of positive constant voltage stress (CVS) on device parameter degradation which may have a potential impact on analog and mixed-signal CMOS circuitry. Significant decrease in g_m and increase in V_t was observed under CVS due to electron trapping.
机译：现代CMOS RF IC设计中的挑战包括优化增益，噪声和线性度。这些参数高度取决于跨导（g_m）和阈值电压（V_t）。在高级CMOS栅极堆叠中引入带有金属栅极的高K电介质需要彻底研究g_m和V_t因应力对RFIC性能造成的任何变化的影响。本文研究了正恒定电压应力（CVS）对器件参数劣化的影响，该影响可能会对模拟和混合信号CMOS电路产生潜在影响。由于电子俘获，在CVS下观察到g_m的显着降低和V_t的显着升高。

著录项

  • 来源
  • 会议地点 Boston MA(US);Boston MA(US)
  • 作者

    P. C. Paliwoda; D. Misra;

  • 作者单位

    Department of Electrical Computing Engineering, New Jersey Institute of Technology, Newark, New Jersey 07102, USA;

    Department of Electrical Computing Engineering, New Jersey Institute of Technology, Newark, New Jersey 07102, USA;

  • 会议组织
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 半导体技术;
  • 关键词

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号