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Growth of InAs/InAIAs Core-Shell Nanowires on Si and Transistor Application

机译：InAs和InAIAs核壳纳米线在Si和晶体管上的生长

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摘要

We review the fabrication process for a surrounding-gate transistor using InAs and InAs/InAIAs core-multishell nanowires (NWs) heterogeneously integrated on Si. Selective-area metalorganic vapor-phase epitaxy (SA-MOVPE) that allows for the position-controlled growth of vertical InAs NWs on (111) oriented surfaces using lithographic techniques was used to grow these nanowires. The nanometer-scale growth enabled for the integration of III-V NWs on Si regardless of apparent lattice mismatches. A non-planar vertical transistor architecture, which is a vertical surrounding-gate structure, was demonstrated on Si substrate. This demonstrated device should have broad applications for use in high-electron mobility transistors with a functionality not made possible using conventional Si-CMOS techniques.
机译：我们审查了异质集成在Si上的InAs和InAs / InAIAs核心-多壳纳米线（NWs）围栅晶体管的制造工艺。选择性区域金属有机气相外延（SA-MOVPE）允许使用光刻技术在（111）取向的表面上垂直控制InAs NW的位置生长，用于生长这些纳米线。纳米级生长使得能够将III-V NW集成到Si上，而不管表观晶格失配如何。在硅衬底上演示了一种非平面垂直晶体管结构，该结构是垂直环绕栅结构。该示范器件应具有广泛的应用，可用于高电子迁移率晶体管，其功能无法使用传统的Si-CMOS技术实现。

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  • 来源
  • 会议地点 Boston MA(US);Boston MA(US)
  • 作者

    Katsuhiro Tomioka; Tomotaka Tanaka; Takashi Fukui;

  • 作者单位

    Graduate School of Information Science and Technology, and Research Center for Integrated Quantum Electronics (RCIQE), Hokkaido University, Sapporo, 060-8628 Hokkaido, Japan,PRESTO, Japan Science and Technology Agency (JST), Kawaguchi, 332-0012 Saitama, Japan;

    Graduate School of Information Science and Technology, and Research Center for Integrated Quantum Electronics (RCIQE), Hokkaido University, Sapporo, 060-8628 Hokkaido, Japan;

    Graduate School of Information Science and Technology, and Research Center for Integrated Quantum Electronics (RCIQE), Hokkaido University, Sapporo, 060-8628 Hokkaido, Japan;

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  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 半导体技术;
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