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Selective-Area Growth of InAs Nanowires on Ge and Vertical Transistor Application

机译：In Ge和垂直晶体管上InAs纳米线的选择性区域生长

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摘要

III-V compound semiconductor and Ge are promising channel materials for future low-power and high-performance integrated circuits. A heterogeneous integration of these materials on the same platform, however, raises serious problem owing to a huge mismatch of carrier mobility. We proposed direct integration of perfectly vertically aligned InAs nanowires on Ge as a method for new alternative integrated circuits and demonstrated a high-performance InAs nanowire-vertical surrounding-gate transistor Virtually 100% yield of vertically aligned InAs nanowires was achieved by controlling the initial surface of Ge and high-quality InAs nanowires were obtained regardless of lattice mismatch (6.7%). The transistor performance showed significantly higher conductivity with good gate control compared to Si-based conventional field-effect transistors: the drain current was 0.65 mA/mu m, and the transconductance was 2.2 mS/mu m at drain-source voltage of 0.50 V. These demonstrations are a first step for building alternative integrated circuits using vertical III-V/multigate planar Ge FETs.
机译：III-V族化合物半导体和Ge是用于未来低功耗和高性能集成电路的有前途的沟道材料。然而，由于载流子迁移率的巨大不匹配，这些材料在同一平台上的异构集成引起了严重的问题。我们提出了在Ge上直接集成完美垂直排列的InAs纳米线的方法，作为一种新的替代集成电路的方法，并演示了一种高性能的InAs纳米线-垂直环绕栅晶体管。通过控制初始表面，几乎可以实现100％的垂直排列InAs纳米线的良率无论晶格失配（6.7％），都能获得Ge和高质量的InAs纳米线。与基于Si的常规场效应晶体管相比，该晶体管的性能表现出明显更高的电导率以及良好的栅极控制：漏极电流为0.55 V时，漏极电流为0.65 mA /μm，跨导为2.2 mS /μm。这些演示是使用垂直III-V /多栅极平面Ge FET构建替代集成电路的第一步。

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