When designing a pipelined single-chip processor (SCP) with pipelined functional units of varying length, the processor issue logic must deal with scheduling of the result bus. In order to prevent serious performance degradation due to result bus conflicts, some pipeline scheduling techniques developed in the 1970's may need to be incorporated into the issue logic. Since this is a non-trivial complication of the issue logic, a set of simulations were performed in order to evaluate the effectiveness of the combination of multiple length functional units and scheduling techniques. Analysis of the simulation results indicates that providing relatively short multiple length functional units is not worthwhile. Multiple length functional unit configurations employing result bus scheduling do perform slightly better than uniform length configurations, but the difference is often less than 1%. Thus, the SCP designer should not waste valuable time improving the performance of each functional unit, but rather should produce a good design for the most complicated unit and design all other units to match it.
当设计具有长度可变的流水线功能单元的流水线单芯片处理器(SCP)时,处理器发出逻辑必须处理结果总线的调度。为了防止由于结果总线冲突导致的严重性能下降,可能需要将1970年代开发的某些管道调度技术并入问题逻辑中。由于这是问题逻辑的一个非常简单的复杂性,因此进行了一组模拟,以评估多长度功能单元和调度技术组合的有效性。对仿真结果的分析表明,提供相对较短的多长度功能单元是不值得的。采用结果总线调度的多长度功能单元配置的确比统一长度配置的性能稍好,但差异通常小于1%。因此,SCP设计师不应浪费宝贵的时间来提高每个功能单元的性能,而应该为最复杂的单元做出好的设计,并设计所有与之匹配的其他单元。 P>
Computer Science Division, University of California, Davis, Davis, CA;
Department of Electrical and Computer Engineering, University of Colorado-Boulder, Boulder, CO;
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