• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>SEM IX International Congress on Experimental Mechanics June 5-8, 2000 Orlando, Florida >Measurement of die stresses in flip chip on laminate assembles
【24h】

Measurement of die stresses in flip chip on laminate assembles

机译：测量层压板组件上倒装芯片中的芯片应力

获取原文
获取原文并翻译 | 示例
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Die cracking is a major failure mode observed during flip chip on laminate assembly or during subsequent package thermal cycling reliability tests. At low temperatures, tensile stresses are produced on the backside of the silicon die due to the nature of the underfill process and the mismatch in coefficients of expansion of the silicon die and laminate substrate. In this work, stress sensing test chips have been used to measure the mechanical stresses on the backside of die in flip chip on laminate assembles. Special piezoresistive test die were fabricated with the sensing resistors on the face of the die opposite to the solder bumps. This is contrary to other studies that have used stress sensors to measure stresses on the device surface of the die (solder bump side). The backside die stresses have been measured after solder reflow, during underfill cure, and as a function of temperature after cure. The experimental stress measurements were then correlated with finite element predictions for the flip chip configurations. Using the measurements and numerical simulations, valuable insight has been gained on die cracking phenomena during flip chip on laminate assembly.
机译：模具开裂是层压板组件上倒装芯片或后续封装热循环可靠性测试期间观察到的主要故障模式。在低温下，由于底部填充工艺的性质以及硅芯片和层压基板的膨胀系数的不匹配，在硅芯片的背面会产生张应力。在这项工作中，应力感应测试芯片已用于测量层压板组件上倒装芯片中芯片背面的机械应力。特殊的压阻测试管芯是在管芯的与焊料凸点相对的面上使用感测电阻器制成的。这与其他使用应力传感器来测量芯片的器件表面（焊锡凸块侧）上的应力的研究相反。在焊料回流之后，底部填充固化期间以及固化后温度的函数中，已经测量了背面芯片应力。然后将实验应力测量值与倒装芯片配置的有限元预测相关联。使用测量和数值模拟，已经获得了在层压板上倒装芯片组装过程中芯片开裂现象的宝贵见解。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号