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首页> 外文会议>Symposium on CMOS Front - End Materials and Process Technology; 20030422-20030424; San Francisco,CA; US >Flat-band Voltage Study Of Atomic-layer-Deposited Aluminum-oxide Subjected To Spike Thermal Annealing
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Flat-band Voltage Study Of Atomic-layer-Deposited Aluminum-oxide Subjected To Spike Thermal Annealing

机译：尖峰热退火的原子层沉积氧化铝的平带电压研究

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摘要

High-κ dielectrics based the oxide of Al were prepared by atomic layer deposition (ALD) on 200-mm p-type Si wafers. Films were deposited directly on clean Si or on 0.5-nm underlayers of rapid thermal oxide or oxynitrides grown in O_2 and/or NO ambients. The purpose of the underlayer films is to provide a barrier for atomic diffusion from the crystal Si to the high-κ dielectric film. Deposited Al-oxide films varied in thickness from 2 to 6 nm. Post deposition anneals were used to stabilize the ALD oxides. Equivalent SiO_2-oxide thickness varied from 1.0 to 3.5 nm. In situ P-doped amorphous-Si 160 nm films were deposited over the oxides to prepare heavily doped n-type gate electrodes in MOS structures. Samples were rapid thermal annealed in N_2 ambient at 800℃ for 30 s, or spike annealed at 950, 1000, and 1050℃ (nominally zero time at peak temperature). Flat band voltages, VFB were determined from C-V measurements on dot patterns. The 800℃ anneals were used as a baseline, at which the poly-Si electrodes are crystallized and acquire electrical activation while subjecting the high-κ dielectrics to a low thermal budget. Positive shifts in V_(FB) were observed, relative to a pure SiO_2 control, ranging from 0.2 to 0.8 V. Spike annealing reduces the V_(FB) shift for ALD films deposited over underlayer films. The V_(FB) shift and the changes with annealing temperature show systematic dependence on the nitridation of the underlayer.
机译：通过在200 mm p型Si晶片上进行原子层沉积（ALD）制备基于Al的高κ电介质。将膜直接沉积在干净的Si上或在O_2和/或NO环境中生长的快速热氧化物或氮氧化物的0.5 nm底层上。底层膜的目的是为从晶体Si到高κ介电膜的原子扩散提供阻挡层。沉积的氧化铝膜的厚度在2到6 nm之间变化。沉积后退火用于稳定ALD氧化物。等效的SiO_2-氧化物厚度在1.0到3.5 nm之间变化。在氧化物上沉积原位P掺杂的非晶硅160 nm薄膜，以制备MOS结构中的重掺杂n型栅电极。将样品在N_2环境中于800℃进行快速热退火30 s，或在950、1000和1050℃进行尖峰退火（在峰值温度下通常为零时间）。平坦带电压VFB由点图案上的C-V测量确定。以800℃退火为基准，在该温度下，多晶硅电极结晶并获得电激活，同时使高κ电介质承受较低的热预算。相对于纯SiO_2控件，观察到V_（FB）的正向位移，范围为0.2至0.8V。尖峰退火降低了沉积在下层膜上的ALD膜的V_（FB）位移。 V_（FB）位移和随退火温度的变化显示出对底层氮化的系统依赖性。

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