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首页> 外文会议>Symposium on CMOS Front - End Materials and Process Technology; 20030422-20030424; San Francisco,CA; US >A Technique for Source/Drain Elevation using Implantation Mediated Selective Etching
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A Technique for Source/Drain Elevation using Implantation Mediated Selective Etching

机译：利用植入介导的选择性刻蚀进行源/漏高程的技术

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摘要

A process involving implantation mediated selective etching has been developed for Source/Drain elevation of CMOS devices. 100 nm thick epitaxial silicon/polysilicon layer was formed on patterned Si/SiO_2 structure by chemical vapor deposition (CVD) at 700℃. Structural damage was selectively introduced in polysilicon layer by a low dose Argon implantation at 140 keV. Crystal damage in epitaxial silicon layer was kept minimum by aligning the implantation in vertical <100> channeling direction. A short duration post-anneal at 420℃ was used for structural recovery of the silicon layer. Polysilicon layer was then removed by wet etching with more than an order of magnitude selectivity over epitaxial silicon. The resulting structure of elevated silicon is free from faceting effects. The process is independent of sidewall/isolation materials, and not bound by thickness limits.
机译：已经开发了一种涉及注入介导的选择性蚀刻的工艺，以用于CMOS器件的源/漏标高。通过化学气相沉积（CVD）在700℃下在图案化的Si / SiO_2结构上形成100nm厚的外延硅/多晶硅层。通过在140 keV的低剂量氩气注入，选择性地将结构损伤引入多晶硅层。通过在垂直<100>沟道方向上对准注入，使外延硅层中的晶体损伤保持最小。在420℃下进行短时间的退火后用于硅层的结构恢复。然后通过湿蚀刻去除多晶硅层，其在外延硅上的选择性大于一个数量级。所得的高架硅结构没有刻面效应。该过程与侧壁/隔离材料无关，并且不受厚度限制的约束。

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