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首页> 外文会议>Symposium Proceedings vol.808; Symposium on Amorphous and Nanocrystalline Silicon Science and Technology - 2004; 20040413-16; San Francisco,CA(US) >Performance analysis of a-Si:H detectors deposited on CMOS chips
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Performance analysis of a-Si:H detectors deposited on CMOS chips

机译：沉积在CMOS芯片上的a-Si：H检测器的性能分析

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摘要

Image and particle sensors based on thin-film on CMOS technology are currently being developed at our laboratory. In this technology, amorphous silicon detectors are vertically integrated on top of dedicated CMOS chips. For both, vision and particle detection, this approach is expected to enhance the performances. In fact very high fill factors, increased sensitivity, and integration level, coupled with extremely low dark current density values can potentially be attained. A first optimization of the a-Si:H diodes ( > 1mm~2) on glass substrates, with the primary focus on reducing dark current densities, gave J_(dark) values as low as 1 pA/cm~2 (at -1 V for 1 μm thick detectors). These detectors were then deposited on CMOS readout chips, but so far this step was unfortunately accompanied by an increase in J_(dark) to values over 10 nA/cm~2. Here, the possible cause for such an increase in J_(dark) as well as possible "remedies" against this effect will be discussed; the principle cause is supposed to be the influence of chip topology. Possible solutions include surface treatments as well as the use of metal-i-p diode configuration. Results obtained so far with these methods are given.
机译：目前，我们实验室正在开发基于CMOS技术薄膜的图像和颗粒传感器。在这项技术中，非晶硅检测器垂直集成在专用CMOS芯片的顶部。对于视觉检测和粒子检测，该方法有望增强性能。实际上，可以潜在地获得很高的填充系数，更高的灵敏度和集成度，以及极低的暗电流密度值。对玻璃基板上的a-Si：H二极管（> 1mm〜2）的首次优化（主要致力于降低暗电流密度）使J_（dark）值低至1 pA / cm〜2（在-1时） V用于1μm厚的检测器）。然后将这些检测器沉积在CMOS读出芯片上，但是到目前为止，不幸的是，此步骤伴随J_（暗）值增加到10 nA / cm〜2以上。在此，将讨论导致J_（dark）增大的可能原因以及针对此效果的可能“补救措施”；主要原因可能是芯片拓扑的影响。可能的解决方案包括表面处理以及使用金属i-p二极管配置。给出了迄今为止使用这些方法获得的结果。

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