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首页> 外文会议>Thirty - first Symposium on State-of-the-Art Program on Compound Semiconductors (SOTAPOCS XXXI), Honolulu, Hawaii; October 17-22, 1999 >Dual-Side wafer processing and resonant tunneling transistor applications
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Dual-Side wafer processing and resonant tunneling transistor applications

机译：双面晶圆处理和共振隧穿晶体管应用

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摘要

We describe dual - side wafer processing and its application to resonant tunneling transistors in a planar configuration. The fabrication technique utilizes a novel flip - chip, wafer thinning process called epoxy-bond and stop - etch (EBASE) process, where the substrate material is removed by selective wet etching and stopped at an etch - stop layer. This EBASE method results in a semiconductor epitaxial layer that is typically less than a micron thick and has a mirror - finish, allowing backside gates to be placed in close proximity to frontside gates. Utilizing this technique, a resonant tunneling transistor - the double electron layer tunneling transistor (DELTT) - can be fabricated in a fully planar configuration, where the tunneling between two selectively - contacted 2DEGs in GaAs or InGaAs quantum wells is modulated by surface Schottky gate. Low temperature electrical characterization yields source - drain I-V curves with a gate - tunable negative differential resistance.
机译：我们描述了双面晶圆处理及其在平面配置中对共振隧穿晶体管的应用。该制造技术利用了一种新颖的倒装芯片，晶圆减薄工艺，称为环氧键合和停止蚀刻（EBASE）工艺，该工艺通过选择性湿蚀刻去除衬底材料，并将其停在蚀刻停止层。这种EBASE方法产生的半导体外延层通常小于一微米厚，并具有镜面光洁度，可以将背面栅极放置在紧邻正面栅极的位置。利用这种技术，可以在完全平面的结构中制造谐振隧穿晶体管-双电子层隧穿晶体管（DELTT），其中GaAs或InGaAs量子阱中两个选择性接触的2DEG之间的隧穿由表面肖特基栅极调制。低温电特性可产生源极-漏极I-V曲线以及栅极-可调负差分电阻。

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