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首页> 外文会议>VLSI signal processing, VIII >ALGORITHM-BASED LOW-POWER DSP SYSTEM DESIGN: METHODOLOGY AND VERIFICATION
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ALGORITHM-BASED LOW-POWER DSP SYSTEM DESIGN: METHODOLOGY AND VERIFICATION

机译：基于算法的低功耗DSP系统设计：方法论与验证

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摘要

We present a low-power design methodology based on the multi-rate approach for DSP systems. Since the data rate in the resulting multirate implementation is M-times slower (where M is a positive integer) than the original data rate while maintaining the same throughput rate, we can apply this feature to either the low-power implementation, or the speed-up of the DSP systems. This design methodology provides VLSI designers a systematic tool to design low-power DSP systems at the algorithmic/architectural level. The proposed low-power multirate design scheme is verified by the implementation of two FIR VLSI chips with different architectures: One is the normal pipelined design and the other is the multirate FIR design with downsampling rate equal to two. Using the CMOS power dissipation model, we can predict that the multirate FIR chip consumes only 29% power of the normal FIR chip given the same throughput rate. The predicted results will be verified by measuring real power consumption of both chips.
机译：我们提出了一种基于多速率DSP系统的低功耗设计方法。由于最终的多速率实现中的数据速率比原始数据速率慢了M倍（其中M是一个正整数），同时保持了相同的吞吐速率，因此我们可以将此功能应用于低功耗实现或速度DSP系统的特写。这种设计方法为VLSI设计人员提供了一种系统的工具，可以在算法/体系结构级别设计低功耗DSP系统。通过采用两种不同架构的FIR VLSI芯片，验证了所提出的低功耗多速率设计方案：一种是常规流水线设计，另一种是下采样率等于2的多速率FIR设计。使用CMOS功耗模型，我们可以预测，在相同的吞吐速率下，多速率FIR芯片仅消耗普通FIR芯片29％的功率。通过测量两个芯片的实际功耗，可以验证预测结果。

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  • 来源
    《VLSI signal processing, VIII》|1995年|277-286|共10页
  • 会议地点 Sakai(JP)
  • 作者

    An-Yeu Wu; K. J. Ray Liu; Zhongying Zhang; Kazuo Nakajima; Arun Raghupathy; Shang-Chieh Liu;

  • 作者单位

    Electrical Engineering University of Maryland College Park, MD 20742 Institute for Systems Research University of Maryland College Park, MD 20742;

    Electrical Engineering University of Maryland College Park, MD 20742 Institute for Systems Research University of Maryland College Park, MD 20742;

    Electrical Engineering University of Maryland College Park, MD 20742;

    Electrical Engineering University of Maryland College Park, MD 20742;

    Electrical Engineering University of Maryland College Park, MD 20742 Institute for Systems Research University of Maryland College Park, MD 20742;

    Electrical Engineering University of Maryland College Park, MD 20742 Institute for Systems Research University of Maryland College Park, MD 20742;

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  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 微电子学、集成电路（IC）;通信理论;
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