Understanding Power Supply Droop during At-Speed Scan Testing

机译：在全速扫描测试中了解电源下垂

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摘要

The paper explores the effects of power-supply droop during scan based at-speed test application. The unnatural supply voltage profile that results when the capture clocks are fired during such tests can lead to artificial failures and bring into question the validity of using structural at-speed testing as a delay defect screen. The experiments described in this paper attempt to fully characterize this effect in a number of different ways. Although the focus of this publication is mainly transition scan patterns, the results are equally applicable to path-delay scan testing.

机译：本文探讨了在基于全速测试的扫描过程中电源下降的影响。在此类测试过程中触发捕获时钟时产生的电源电压异常会导致人为故障，并质疑使用结构化快速测试作为延迟缺陷筛选的有效性。本文描述的实验试图以多种不同方式完全表征这种效应。尽管本出版物的重点主要是过渡扫描模式，但结果同样适用于路径延迟扫描测试。

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来源
《VLSI Test Symposium, 2009. VTS '09》|2009年|227-232|共6页
会议地点 Santa Cruz CA(US);Santa Cruz CA(US)
作者
Pant P.; Zelman J.;
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作者单位

Intel Corp., Hudson, MA, USA;

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关键词
clocks; integrated circuit testing; microprocessor chips; power supply circuits; Intel microprocessor; artificial failures; at-speed scan testing; capture clocks; path-delay scan testing; power-supply droop; unnatural supply voltage profile; At-speed scan; functional test correlation; power supply droop;

机译：时钟;集成电路测试;微处理器芯片;电源电路;英特尔微处理器;人为故障;全速扫描测试;捕获时钟;路径延迟扫描测试;电源下垂;电源电压分布不自然;全速扫描;功能正常测试相关性;电源下垂;

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1. Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment [J] . Wu M.-F., Huang J.-L., Wen X., Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on . 2009,第11期

机译：降低线性降压环境中全速扫描测试的电源噪声
2. Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing [J] . Li Y.-H., Lien W.-C., Lin I.-C., IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2014,第1期

机译：捕获功率安全的测试模式确定，用于基于扫描的全速测试
3. X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing [J] . Li J., Xu Q., Hu Y., Very Large Scale Integration (VLSI) Systems, IEEE Transactions on . 2010,第7期

机译：X-Filling可在基于扫描的高速测试中同时降低移位和捕获功率
4. Understanding Power Supply Droop During At-Speed Scan Testing [C] . Pankaj Pant, Joshua Zelman IEEE VLSI Test Symposium . 2009

机译：在速度扫描测试期间了解电源下垂
5. Low cost power and supply noise estimation and control in scan testing of VLSI circuits [D] . Jiang, Zhongwei 2010

机译：VLSI电路扫描测试中的低成本电源和电源噪声估计与控制
6. A powerful score test to detect positive selection in genome-wide scans [O] . Ming Zhong, Kenneth Lange, Jeanette C Papp, 2010

机译：功能强大的分数测试可检测全基因组扫描中的阳性选择
7. Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment [O] . Wu Meng-Fan, Huang Jiun-Lang, Wen Xiaoqing, 2009

机译：降低线性降压环境中全速扫描测试的电源噪声

Understanding Power Supply Droop during At-Speed Scan Testing

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