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首页> 外文会议>World Tribology Congress III 2005 vol.2 >GLOBAL PLANARIZATION REQUIREMENTS FOR WAFER-LEVEL THREE-DIMENSIONAL (3D) ICS
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GLOBAL PLANARIZATION REQUIREMENTS FOR WAFER-LEVEL THREE-DIMENSIONAL (3D) ICS

机译：晶圆级三维（3D）ICS的全球规划要求

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摘要

Planarization needs for integrated circuit (IC) technology focus on feature-scale (100nm-1μm) and die-scale (5mm-20mm) dimensions. As three-dimensional (3D) integration moves from die-by-die assembly to wafer-level integration to provide a higher density of low electrical parasitic vertical interconnects (or vias), wafer-level planarization needs to be considered. Planarization needs depend upon the 3D technology platform approach (such as (1) blanket bonding followed by inter-wafer interconnect processing or via-first processing followed by bonding and thinning to expose the vias and (2) the number of wafers in a 3D stack) and the processing conditions used in fabricating the wafers to be 3D integrated (in particular, the built-in stress levels and post-bonding thermal processing budget). This invited presentation includes a summary of the current interest in wafer-level 3D integration in both the academic and industrial research community. Wafer-level planarization issues with different technology platforms are presented, and the limited results presented in the literature to date are summarized. The importance of wafer-level planarization compared to bonding, thinning and wafer-to-wafer alignment is discussed.
机译：集成电路（IC）技术的平面化需求集中在特征尺寸（100nm-1μm）和管芯尺寸（5mm-20mm）尺寸上。随着三维（3D）集成从逐个管芯的组装转移到晶圆级集成，以提供更高密度的低电寄生垂直互连（或过孔），需要考虑晶圆级平面化。平面化需求取决于3D技术平台方法（例如（1）毯式键合，然后进行晶片间互连处理，或者先进行过孔处理，然后进行键合和薄化以暴露出过孔；（2）3D堆栈中的晶片数量）以及用于制造要进行3D集成的晶圆的处理条件（特别是内置应力水平和键合后热处理预算）。此次受邀的演讲总结了学术界和工业研究界对晶圆级3D集成的当前兴趣。提出了具有不同技术平台的晶圆级平面化问题，并总结了迄今为止在文献中提出的有限结果。讨论了与键合，薄化和晶圆间对准相比，晶圆级平面化的重要性。

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