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Efficiency enhancement techniques for CMOS RF power amplifiers.

机译：CMOS RF功率放大器的效率增强技术。

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摘要

Growth in the wireless communication market in recent years has been driving the demand for higher integration of CMOS wireless transceivers in order to achieve lower cost, smaller form factor, and more functionalities. Much recent research effort has demonstrated the feasibility to integrate most transceiver building blocks into a single CMOS die. One of the few remaining blocks that has yet to be successfully integrated is the Power Amplifier (PA). The PA is usually the last active building block in a radio transmitter. Its function is to amplify the signal power up to the required level before it can be transmitted into the air. Due to several limitations of CMOS technology, designing a linear and efficient PA is a challenging task.; A property shared among most PAs is that the maximum power efficiency is achieved only when the PA is transmitting peak output power. Efficiency degrades dramatically as output power decreases. Under typical operating conditions, the PA transmits well below its peak output power, therefore the 1 effective efficiency is much lower than the maximum value. This thesis applies a concept first developed in the vacuum tube era by William H. Doherty to improve amplifier efficiency over a wide range of output power to the CMOS PA problem. Several circuit techniques are also explored in order to optimize efficiency and linearity of CMOS PA, and to allow a high level of integration.; A highly integrated PA prototype was designed in a 0.13mum CMOS technology. It is designed to operate in the cellular DCS1800 band, which has the transmit frequency between 1710MHz and 1785MHz. With GMSK modulated signal, the prototype achieves +31.8dBm output power with 36% power-added efficiency (PAE). The PAE stays above 18% over 10dB range of output power. The PA also meets the GSM/EDGE spectral mask requirement at +25dBm output power with 13% PAE.
机译：近年来，无线通信市场的增长推动了对CMOS无线收发器更高集成度的需求，以实现更低的成本，更小的外形尺寸和更多的功能。最近的大量研究表明，将大多数收发器构建模块集成到单个CMOS芯片中的可行性。功率放大器（PA）是尚待成功集成的少数几个模块之一。 PA通常是无线电发射机中最后一个活动的构建块。其功能是将信号功率放大到所需水平，然后再将其传输到空中。由于CMOS技术的一些局限性，设计线性高效的PA是一项艰巨的任务。大多数PA之间共享的一个特性是，只有在PA传输峰值输出功率时才能实现最大功率效率。效率随着输出功率的降低而急剧下降。在典型的工作条件下，功率放大器的发射功率远低于其峰值输出功率，因此1有效效率远低于最大值。本文采用了William H. Doherty在真空管时代首次提出的概念，以在广泛的输出功率范围内提高CMOS PA问题的放大器效率。还探索了几种电路技术，以优化CMOS PA的效率和线性度，并实现高集成度。采用0.13μmCMOS技术设计了高度集成的PA原型。它被设计为在蜂窝DCS1800频带中运行，该频带的发射频率在1710MHz和1785MHz之间。利用GMSK调制信号，该原型可实现+ 31.8dBm的输出功率，并具有36％的功率附加效率（PAE）。在10dB的输出功率范围内，PAE保持在18％以上。功率放大器还以13％的PAE满足+ 25dBm输出功率下的GSM / EDGE频谱模板要求。

著录项

  • 作者

    Wongkomet, Naratip.;

  • 作者单位

    University of California, Berkeley.;

  • 授予单位 University of California, Berkeley.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2006
  • 页码 148 p.
  • 总页数 148
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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