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Metal-oxide-semiconductor field effect nanostructure spin lattice devices.

机译：金属氧化物半导体场效应纳米结构自旋晶格器件。

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摘要

This dissertation explored and developed technologies for silicon based spin lattice devices. Spin lattices are artificial electron spin systems with a periodic structure having one to a few electrons at each site. They are expected to have various magnetic and even superconducting properties when structured at an optimal scale with a specific number i of electrons. Silicon turns out to be a very good material choice in realizing spin lattices. A metal-oxide-semiconductor field-effect nanostructure (MOSFENS) device, which is closely related to a MOS transistor but with a nanostructured oxide-semiconductor interface, can define the spin lattices potential at the interface and alter the occupation i with the gate electrode potential to change the magnetic phase. The MOSFENS spin lattices engineering challenge addressed in this work has come from the practical difficulty of process integration in modifying a transistor fabrication process to accommodate the interface patterning requirements.;Two distinct design choices for the fabrication sequences that create the nanostructure have been examined. Patterning the silicon surface before the MOS gate stack layers gives a "nanostructure first" process, and patterning the interface after forming the gate stack gives a "nanostructure last process." Both processes take advantage of a nano-LOCOS (nano-local oxidation of silicon) invention developed in this work. The nano-LOCOS process plays a central role in defining a clean, sharp confining potential for the spin lattice electrons.;The MOSFENS process required a basic transistor fabrication process that can accommodate the nanostructures. The process developed for this purpose has a gate stack with a 15 nm polysilicon gate electrode and a 3 nm thermal gate oxide on a p-type silicon substrate. The measured threshold voltage is 0.25 V. Device processes were examined for either isolating the devices with windows in the field oxide or with mesas defined by the etched trenches filled with oxide.;The nanostructrure patterning processes combined electron beam lithography, reactive ion etching and the nano-LOCOS in a nanostructure last fabrication sequence. The electron beam tool produced holes with diameters down to 10 nm and lattice periods down to 50 nm for defining the spin lattices. The dry etching process was able to transfer the pattern into the polysilicon gate material, and the depth was controlled using the measured etching rate. These dimensions are sufficiently small for spin lattices properties to be important at low temperatures.;Upon combining the NMOS and the nanostructure last processes, MOSFENS spin lattice devices were successfully fabricated. The gates are patterned with lattices having a 50 nm period and 20 nm holes, which is the optimal, targeted ratio of 2.5 for superconductivity. The room temperature current-voltage characteristics of these devices show that the lattice nanostructures significantly reduce the average channel mobility, as expected. However, the essentially unchanged threshold voltage indicates the nano-LOCOS process has given a low-defect nanostructure interface. At room temperature, a change in gate potential of approximately of 18 mV changes the lattice electron occupation from nu = 1 to nu = 2. For these devices, the predicted temperature scale for superconductivity is approximately at 9 K.
机译：本文对硅基自旋晶格器件进行了探索和发展。自旋晶格是具有周期结构的人造电子自旋系统，在每个位点具有一个至几个电子。当以特定数量的i电子以最佳比例进行结构化时，它们有望具有各种磁性甚至超导特性。在实现自旋晶格方面，硅被证明是非常好的材料选择。与MOS晶体管密切相关但具有纳米结构的氧化物-半导体界面的金属氧化物半导体场效应纳米结构（MOSFENS）器件可以定义界面处的自旋晶格电位并改变栅电极的占有率i改变磁性相的潜力。在这项工作中解决的MOSFENS自旋晶格工程挑战来自工艺集成在修改晶体管制造工艺以适应界面图案化要求方面的实际困难。;已经研究了用于创建纳米结构的制造顺序的两种不同的设计选择。在MOS栅极叠层之前对硅表面进行构图可以实现“纳米结构优先”工艺，在形成栅极叠层之后对界面进行构图可以实现“纳米结构后工艺”。两种方法都利用了这项工作中开发的纳米LOCOS（硅的纳米局部氧化）发明。纳米LOCOS工艺在定义自旋晶格电子的清洁，尖锐的限制电位方面起着核心作用。MOSFENS工艺要求基本的晶体管制造工艺能够容纳纳米结构。为此目的开发的工艺具有在p型硅衬底上具有15 nm多晶硅栅电极和3 nm热栅氧化物的栅堆叠。测得的阈值电压为0.25 V.对器件工艺进行了检查，以隔离具有场氧化层中的窗口或由填充有氧化物的蚀刻沟槽所定义的台面的器件。 nano-LOCOS在纳米结构中的最后制造顺序。电子束工具产生了直径低至10 nm的孔和低至50 nm的晶格周期，以定义自旋晶格。干蚀刻工艺能够将图案转移到多晶硅栅极材料中，并且使用测得的蚀刻速率来控制深度。这些尺寸足够小，以至于在低温下对自旋晶格的性能很重要。通过结合NMOS和纳米结构的最后工艺，成功制造了MOSFENS自旋晶格器件。用具有50 nm周期和20 nm孔的晶格对栅极进行构图，这对于超导性来说是2.5的最佳目标比例。这些设备的室温电流-电压特性表明，晶格纳米结构显着降低了平均沟道迁移率，正如预期的那样。然而，基本不变的阈值电压表明纳米LOCOS工艺已经给出了低缺陷的纳米结构界面。在室温下，大约18 mV的栅极电势变化将晶格电子占有率从nu = 1更改为nu =2。对于这些器件，超导的预测温度范围约为9K。

著录项

  • 作者

    Yang, Jun.;

  • 作者单位

    The University of Utah.;

  • 授予单位 The University of Utah.;
  • 学科 Nanoscience.;Nanotechnology.;Physics Quantum.
  • 学位 Ph.D.
  • 年度 2013
  • 页码 102 p.
  • 总页数 102
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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