CMOS bandgap reference circuit.

机译：CMOS带隙基准电路。

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This thesis explores the basic cause of weak gain in conventional folded cascode CMOS OTA, and proposes a novel structure for implementation in a 1-V current mode bandgap reference circuit, which enhances open loop gain by 10 dB. Simulations show that the proposed 0.18 mum, 1-V, 25 muW PMOS input folded cascode OTA achieves an open loop gain and unity gain bandwidth of 80 dB and 50 MHz, respectively.; When the input power supply changes from 1 to 3 V and the temperature changes from 0 to 100°C, simulations for the 1-V current mode bandgap reference circuit using the proposed PMOS input folded cascode CMOS OTA show a TCF of 27.5 ppm/°C, a line regulation of 0.0014, an overall accuracy of 0.275%, and a power supply rejection ratio of 50 dB at 10 KHz.; The proposed 1-V folded cascode CMOS OTA is very suitable for low power applications such as filters and high-performance analog processing circuits. The proposed 1-V current mode bandgap reference circuit has the potential to establish a reference voltage for analog-to-digital and digital-to-analog converters and to provide a biasing voltage for other circuits that is insensitive to the power supply and temperature. (Abstract shortened by UMI.)

机译：本文探究了传统折叠式共源共栅CMOS OTA增益弱的根本原因，并提出了一种在1-V电流模式带隙基准电路中实现的新颖结构，该结构可将开环增益提高10 dB。仿真表明，拟议的0.18μm，1V，25μWPMOS输入折叠共源共栅共基放大器OTA分别实现了80dB和50MHz的开环增益和单位增益带宽。当输入电源从1变为3 V，温度从0变为100°C时，使用建议的PMOS输入折叠共源共栅CMOS OTA对1V电流模式带隙基准电路进行的仿真显示，TCF为27.5 ppm /° C，线路调整率为0.0014，总精度为0.275％，在10 KHz时的电源抑制比为50 dB。拟议的1V折叠共源共栅CMOS OTA非常适合于低功耗应用，例如滤波器和高性能模拟处理电路。拟议的1V电流模式带隙基准电路有可能为模数转换器和数模转换器建立基准电压，并为其他对电源和温度不敏感的电路提供偏置电压。（摘要由UMI缩短。）

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作者
Ge, Lei.;
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作者单位

Dalhousie University (Canada).;

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授予单位 Dalhousie University (Canada).;
学科 Engineering Electronics and Electrical.
学位 M.A.Sc.
年度 2004
页码 112 p.
总页数 112
原文格式 PDF
正文语种 eng
中图分类无线电电子学、电信技术;
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专利

1. Design of Bandgap Core and Startup Circuits for All CMOS Bandgap Voltage Reference [J] . Saweth HONGPRASIT, Worawat SA-NGIAMVIBOOL, Apinan AURASOPON Przeglad Elektrotechniczny . 2012,第4a期

机译：所有CMOS带隙基准电压源的带隙核心和启动电路设计
2. Resistorless BJT bias and curvature compensation circuit at 3.4 nW for CMOS bandgap voltage references [J] . Mattia O.E., Klimach H., Bampi S. Electronics Letters . 2014,第12期

机译：CMOS带隙基准电压源的无电阻BJT偏置和曲率补偿电路（3.4nW）
3. CMOS Bandgap References With Self-Biased Symmetrically Matched Current–Voltage Mirror and Extension of Sub-1-V Design [J] . Lam Y.-H., Ki W.-H. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on . 2010,第6期

机译：具有自偏置对称匹配电流电压镜的CMOS带隙基准和Sub-1V设计的扩展
4. Low voltage CMOS bandgap references with temperature compensated reference current output [C] . Lee Edward K. F. Proceedings of 2010 IEEE International Symposium on Circuits and Systems . 2010

机译：具有温度补偿参考电流输出的低压CMOS带隙参考
5. An accurate, trimless, high PSRR, low-voltage, CMOS bandgap reference IC. [D] . Gupta, Vishal. 2007

机译：一款精确，无扰动，高PSRR，低压，CMOS带隙基准IC。
6. Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference [O] . El Hafed Boufouss, Laurent A. Francis, Valeriya Kilchytska, 2013

机译：超低功率高温和辐射硬互补金属氧化物半导体（CMOS）绝缘体上硅（SOI）电压基准
7. A Power- and Area-Efficient CMOS Bandgap Reference Circuit with an Integrated Voltage-Reference Branch [O] . Santunu Sarangi, Dhananjaya Tripathy, Subhra Sutapa Mahapatra, 2020

机译：具有集成电压参考分支的功率和区域高效的CMOS带隙参考电路

CMOS bandgap reference circuit.

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