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Post layout validation of discrete gate sizing and VT selection.

机译:离散栅极尺寸和VT选择的布局后验证。

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摘要

Many algorithms for gate size and threshold voltage (VT) optimization have been proposed. The International Symposium of Physical Design (ISPD) contests for discrete gate sizing with wire loads have led to improved algorithms. Significant changes in cell sizes require re-placement and re-routing which invalidate the wire loads upon which the sizing was performed. In turn, sizing must be re-performed with new wire loads. To best of our knowledge, it has not been shown how much leakage power reduction can be obtained for actually laid out circuits, nor whether the process even converges. In this work, we chose a gate size and VT optimization algorithm which achieves leakage reduction results comparable to best reported to date for smaller circuits and better results for the largest circuits in the ISPD set. We interfaced the tool with leading EDA tools using a 45nm multi-VT cell library. We propose an incremental placement and routing methodology for use with the EDA placement and routing tool, such that the post-sizing placement and routing converges to the optimization achieved after sizing. The flow achieves as much as 28% leakage reduction with an average reduction of 12% after performing the proposed incremental placement and routing.
机译:已经提出了许多用于栅极尺寸和阈值电压(VT)优化的算法。国际物理设计研讨会(ISPD)竞赛针对具有线负载的离散浇口尺寸进行了改进,从而改进了算法。单元尺寸的重大变化需要重新放置和重新布线,这会使在其上施胶的导线负载无效。反过来,必须在新的电线负载下重新进行尺寸调整。据我们所知,尚未显示出对于实际布置的电路可以减少多少泄漏功率,或者该过程是否收敛。在这项工作中,我们选择了门的尺寸和VT优化算法,该算法可实现的泄漏减少效果可与迄今为止针对较小电路的最佳报告和针对ISPD集中最大电路的更好结果相媲美。我们使用45nm多重VT单元库将该工具与领先的EDA工具进行了接口。我们提出一种与EDA布局和布线工具一起使用的增量布局和布线方法,以使调整后的布局和布线收敛到调整后实现的优化。在执行建议的增量式放置和布线后,该流可实现多达28%的泄漏减少,平均减少12%。

著录项

  • 作者单位

    The University of Texas at Dallas.;

  • 授予单位 The University of Texas at Dallas.;
  • 学科 Electrical engineering.
  • 学位 M.S.E.E.
  • 年度 2016
  • 页码 72 p.
  • 总页数 72
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 康复医学;
  • 关键词

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