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High-k gate dielectrics for silicon CMOS applications.

机译：用于硅CMOS应用的高k栅极电介质。

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摘要

This thesis focuses on the understanding of many fundamental properties of high-k gate dielectrics for Si CMOS gate applications, and on the development of ultra-thin ZrO2/Zr silicate, titanium aluminates, and TiO 2/SiN gate dielectrics.; The results demonstrate that the ultra-thin ZrO2/Zr silicate films deposited by the JVD process can have EOTs down to 1 nm, and possess high thermal stability, among other good electrical properties. The presence of a thermally stable Zr silicate interfacial layer may prevent the formation of interfacial silicon oxide during anneal.; Our results also reveal that either incorporating Al into TiO2, or using a high-quality ultra-thin JVD SiN layer can improve the properties of the gate stack after high temperature annealing. The nano-crystallization of titanium aluminates results in considerable degradation of transconductance and reliability.; The barrier heights over Si conduction band edge and conduction mechanisms of several scientifically and technically important high-k materials have been studied. Our results reveal that (1) Though Ta2O 5 possesses a larger bandgap than that of TiO2, due to its adverse band alignment to Si band, Ta2O5 only has a barrier height of 0.28 eV over Si conduction band edge, which is much smaller than that of TiO2. Therefore, Schottky emission or thermionic emission becomes the dominant conduction mechanism in over the Ta2O 5 barrier; (2) The high barrier height of 3.0 eV for ALD Al 2O3 over Si conduction band edge makes it attractive to block thermionic current at elevated temperatures; The barrier height of 2.1 eV for JVD ZrO2/Silicate over the Si conduction band edge is sufficient to block thermionic current; (3) Incorporating Al into TiO2 increases the barrier height of TiO2 over the Si conduction band edge; (4) The work function of 4.7 eV for Tungsten makes its Fermi-level at the mid-gap of Si band.; Through the course of this dissertation study, we have found that (1) it is possible to make MOSFETs with high-k gate dielectrics with mobilities that fit closely to the universal mobility curve, (2) a major portion of the reduced transconductance or conductance can be attributed to trapping, (3) among MOSFET's with Hf silicate, HfO2, and Hf aluminate, the device with Hf silicate shows the highest transconductance and lowest trap densities.
机译：本文着重于了解用于CMOS硅应用的高k栅极电介质的许多基本性能，以及超薄ZrO 2 / Zr硅酸盐，铝酸钛和TiO 2 / SiN栅极电介质。结果表明，通过JVD工艺沉积的超薄ZrO 2 / Zr硅酸盐薄膜可具有低至1 nm的EOT，并具有较高的热稳定性，以及良好的电性能。热稳定的Zr硅酸盐界面层的存在可防止退火期间界面氧化硅的形成。我们的结果还表明，将Al掺入TiO 2 或使用高质量的超薄JVD SiN层可以改善高温退火后的栅极叠层的性能。铝酸钛的纳米结晶导致跨导和可靠性的显着降低。已经研究了几种具有科学和技术重要性的高k材料在Si导带边缘的势垒高度和导电机理。我们的结果表明（1）尽管Ta 2 O 5 具有比TiO 2 大的带隙，这是由于Ta 2 O 5 Si带Ta 2 O 5 在Si导带边缘仅具有0.28 eV的势垒高度，远小于TiO 2 。因此，在Ta 2 O 5 势垒中，肖特基发射或热电子发射成为主要的传导机制。 （2）在Si导带边缘上的ALD Al 2 O 3 具有3.0 eV的高势垒高度，因此在高温下阻挡热电子电流具有吸引力; Si导带边缘上的JVD ZrO 2 / Silicate的势垒高度为2.1 eV，足以阻挡热电子电流。 （3）将Al掺入TiO 2 会增加TiO 2 在Si导带边缘的势垒高度; （4）钨的4.7 eV功函数使其费米能级在Si带的中间带隙处;通过本论文的研究过程，我们发现（1）可以制造迁移率与通用迁移率曲线紧密匹配的高k栅极电介质MOSFET，（2）降低的跨导或电导的主要部分可以归因于俘获，（3）在具有Hf硅酸盐，HfO 2 和Hf铝酸盐的MOSFET中，具有Hf硅酸盐的器件显示出最高的跨导和最低的陷阱密度。

著录项

  • 作者

    Luo, Zhijiong.;

  • 作者单位

    Yale University.;

  • 授予单位 Yale University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2003
  • 页码 218 p.
  • 总页数 218
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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