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Digital background calibration of time-interleaved analog-to-digital converters.

机译：时间交错的模数转换器的数字背景校准。

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摘要

Digital signal processing (DSP) systems operating on analog inputs are often limited by the speed of the analog-to-digital (A/D) interface. With a given process, the maximum sample rate at which a given analog-to-digital converter (ADC) will operate is limited for a given resolution. A well-known technique that can be used to increase the maximum sample rate of ADCs is time-interleaving more than one ADC [1]. Since time-interleaving requires two or more channels in parallel, there are some disadvantages. In addition to increases in area and power, the disadvantages include sensitivity to offset and gain mismatches, and sample-time errors between the individual channels. An adaptive digital background calibration technique is introduced in this thesis to reduce the effects of offset and gain mismatches, and sample-time errors between the time-interleaved channels.; Background calibration is used because it can track variations of offset and gain mismatches, and sample-time errors over time, temperature, and process; that is, during normal ADC operation. The background calibration technique presented has no effect on the input signal bandwidth and eliminates the difference in interference during calibration and conversion modes that may be associated with foreground calibration. Although analog background calibration techniques can be used, digital background calibration is used here because digital circuitry can be scaled with technology and keep the calibration functionality intact.; To demonstrate the digital background calibration approach, a prototype 10-bit 120 MS/s, two-channel parallel pipelined ADC has been designed and fabricated in a 0.35-μm CMOS process. The digital calibration algorithm uses the input signal itself to calibrate for gain mismatches and sample-time errors. The offset calibration algorithm uses random chopping to avoid holes in the ADC output spectrum.; Test results show that the ADC system achieves a peak SNDR of 56.8 dB for a 0.99 MHz sinusoidal input, a peak INL of −0.88 LSB, and peak DNL of +0.44 LSB. The 5.17 mm2 IC dissipates 234 mW from a 3.3 V supply.
机译：在模拟输入上运行的数字信号处理（DSP）系统通常受到模数（A / D）接口速度的限制。对于给定的分辨率，给定的模数转换器（ADC）将以最大采样率运行。可以用来增加ADC的最大采样率的一种众所周知的技术是时间交织多个ADC [1]。由于时间交织需要并行的两个或更多信道，因此存在一些缺点。除了增加面积和功率之外，缺点还包括对失调和增益失配的敏感性以及各个通道之间的采样时间误差。为了减少失调和增益失配以及时间交错通道之间的采样时间误差的影响，本文引入了一种自适应数字背景校准技术。使用背景校准是因为它可以跟踪失调和增益失配的变化，以及随时间，温度和工艺的采样时间误差。也就是说，在正常ADC操作期间。提出的背景校准技术对输入信号带宽没有影响，并消除了可能与前景校准相关的校准和转换模式期间的干扰差异。尽管可以使用模拟背景校准技术，但由于可以使用技术缩放数字电路并保持校准功能完整，因此这里使用数字背景校准。为了演示数字背景校准方法，已经设计出了原型机10位120 MS / s，两通道并行流水线ADC，并采用0.35μmCMOS工艺制造。数字校准算法使用输入信号本身来校准增益失配和采样时间误差。失调校准算法使用随机斩波来避免ADC输出频谱中的空洞。测试结果表明，对于0.99 MHz正弦波输入，ADC系统实现了56.8 dB的峰值SNDR，-0.88 LSB的INL峰值和+0.44 LSB的DNL峰值。 5.17 mm 2 IC的3.3 V电源耗散234 mW。

著录项

  • 作者

    Jamal, Shafiq Mohammad.;

  • 作者单位

    University of California, Davis.;

  • 授予单位 University of California, Davis.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2001
  • 页码 117 p.
  • 总页数 117
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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