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Advances in electronic packaging technologies by ultra-small microvias, super-fine interconnections and low loss polymer dielectrics.

机译：超小型微通孔，超细互连和低损耗聚合物电介质在电子封装技术方面的进步。

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摘要

The fundamental motivation for this dissertation is to address the widening interconnect gap between integrated circuit (IC) demands and package substrates specifically for high frequency digital-RF systems applications. Moore's law for CMOS ICs predicts that transistor density on ICs will double approximately every 18 months. Packaging of ICs at the 32nm and 22nm nodes in the next few years will require 20mum (peripheral) and 80mum (area array) I/O pad pitch on the IC, which must be matched by flip-chip interconnection and substrate wiring pad pitch of the same 20-80mum dimension. System on a Package (SOP) technology pioneered by Georgia Tech PRC enables future "mega-function" electronic and bio-electronic systems through ultra-thin film component integration from the current 50/cm2 to over 10000/cm2. This puts added wiring density and performance demands on the substrate. The other driving force in this thesis research is the increasing adoption of high frequency wireless and wired communication pushing the need for package substrate materials that are stable into multiple GHz frequencies. The current state-of-the-art in IC package substrates is at 20mum lines/spaces and 50-60mum microvia diameter using epoxy dielectrics with loss tangent above 0.01. The research targets are to overcome the barriers of current technologies and demonstrate a set of advanced materials and process technologies capable of 5-10mum lines and spaces, and 10-30mum diameter microvias in a multilayer 3-D wiring substrate using 10-25mum thin film dielectrics with loss tangent in the 0.005. The research elements are organized as follows with a clear focus on understanding and characterization of fundamental materials structure-processing-property relationships and interfaces to achieve the next generation targets: (1) Low CTE Core Substrate. (2) Low Loss Dielectrics with 25mum and smaller microvias. (3) Sub-10mum Width Cu Conductors. (4) Integration of the various dielectric and conductor processes.
机译：本论文的基本动机是解决集成电路（IC）需求与封装衬底之间不断扩大的互连间隙，特别是针对高频数字RF系统应用。 CMOS IC的摩尔定律预测，IC上的晶体管密度大约每18个月就会增加一倍。未来几年，在32nm和22nm节点上封装IC时，IC上需要20mum（外围）和80mum（区域阵列）的I / O焊盘间距，这必须与倒装芯片互连和基板布线焊盘间距相匹配。相同的20-80mm尺寸。乔治亚理工大学率先推出的系统级封装（SOP）技术通过将超薄薄膜组件集成从目前的50 / cm2扩展到10000 / cm2以上，实现了未来的“超多功能”电子和生物电子系统。这对基板增加了布线密度和性能要求。本论文研究的另一个驱动力是高频无线和有线通信的日益普及，这推动了对稳定在多个GHz频率的封装基板材料的需求。使用损耗正切损耗大于0.01的环氧电介质，IC封装衬底中的最新技术为20mum线/间距和50-60mum微通径。研究目标是克服现有技术的障碍，并展示一套先进的材料和工艺技术，这些材料和工艺技术能够在使用10-25mum薄膜的多层3-D布线基板中形成5-10mum的线和间距以及10-30mmm的直径微孔。损耗角正切值小于0.005的电介质。研究要素的组织如下，重点是基本材料的结构，加工，特性关系和界面的理解和表征，以实现下一代目标：（1）低CTE核心基板。 （2）具有25μm和较小微通孔的低损耗电介质。 （3）10mm以下宽度的铜导体。 （4）各种介电和导体工艺的集成。

著录项

  • 作者

    Sundaram, Venkatesh.;

  • 作者单位

    Georgia Institute of Technology.;

  • 授予单位 Georgia Institute of Technology.;
  • 学科 Engineering Materials Science.
  • 学位 Ph.D.
  • 年度 2009
  • 页码 203 p.
  • 总页数 203
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 工程材料学;
  • 关键词

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