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Polymorphic chip multiprocessor architecture.

机译：多态芯片多处理器体系结构。

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摘要

Over the last several years uniprocessor performance scaling slowed significantly because of power dissipation limits and the exhausted benefits of deeper pipelining and instruction-level parallelism. To continue scaling performance, microprocessor designers switched to Chip Multi-Processors (CMP). Now the key issue for continued performance scaling is the development of parallel software applications that can exploit their performance potential. Because the development of such applications using traditional shared memory programming models is difficult, researchers have proposed new parallel programming models such as streaming and transactions. While these models are attractive for certain types of applications they are likely to co-exist with existing shared memory applications.;We designed a polymorphic Chip Multi-Processor architecture, called Smart Memories, which can be configured to work in any of these three programming models. The design of the Smart Memories architecture is based on the observation that the difference between these programming models is in the semantics of memory operations. Thus, the focus of the Smart Memories project was on the design of a reconfigurable memory system. All memory systems have the same fundamental hardware resources such as data storage and interconnect. They differ in the control logic and how the control state associated with the data is manipulated. The Smart Memories architecture combines reconfigurable memory blocks, which have data storage and metadata bits used for control state, and programmable protocol controllers, to map shared memory, streaming, and transactional models with little overhead. Our results show that the Smart Memories architecture achieves good performance scalability. We also designed a test chip which is an implementation of Smart Memories architecture. It contains eight Tensilica processors and the reconfigurable memory system. The dominant overhead was from the use of flops to create some of the specialized memory structures that we required. Since previous work has shown this overhead can be made small, our test-chip confirmed that hardware overhead for reconfigurability would be modest.;This thesis describes the polymorphic Smart Memories architecture and how three different models---shared memory, streaming and transactions---can be mapped onto it, and presents performance evaluation results for applications written for these three models. We found that the flexibility of the Smart Memories architecture has other benefits in addition to better performance. It helped to simplify and optimize complex software runtime systems such as Stream Virtual Machine or transactional runtime, and can be used for various semantic extensions of a particular programming model. For example, we implemented fast synchronization operations in the shared memory mode which utilize metadata bits associated with data word for fine-grain locks.
机译：在过去的几年中，由于功耗限制以及更深层次的流水线技术和指令级并行性的穷尽利益，单处理器性能的扩展速度大大降低。为了继续扩展性能，微处理器设计人员改用了芯片多处理器（CMP）。现在，持续扩展性能的关键问题是开发可以利用其性能潜力的并行软件应用程序。由于使用传统的共享内存编程模型来开发此类应用程序很困难，因此研究人员提出了新的并行编程模型，例如流和事务。尽管这些模型对于某些类型的应用程序很有吸引力，但它们很可能与现有的共享内存应用程序共存。我们设计了一种称为Smart Memories的多态芯片多处理器体系结构，可以将其配置为可在这三种编程中的任何一种下工作楷模。智能内存体系结构的设计基于以下观察：这些编程模型之间的差异在于内存操作的语义。因此，“智能内存”项目的重点是可重配置内存系统的设计。所有内存系统都具有相同的基本硬件资源，例如数据存储和互连。它们在控制逻辑以及与数据关联的控制状态的操纵方式方面有所不同。 Smart Memories体系结构结合了可重配置的存储块，这些存储块具有用于控制状态的数据存储和元数据位以及可编程协议控制器，从而以很少的开销映射共享的内存，流和事务模型。我们的结果表明，智能内存体系结构实现了良好的性能可伸缩性。我们还设计了一种测试芯片，该芯片是Smart Memories体系结构的一种实现。它包含八个Tensilica处理器和可重新配置的内存系统。主要的开销来自使用触发器来创建我们所需的一些专用存储器结构。由于以前的工作表明可以减少这种开销，因此我们的测试芯片证实，用于可重配置性的硬件开销将不大。本文描述了多态智能内存架构以及共享内存，流式传输和事务处理这三种不同模型的方式。 -可以映射到它，并提供针对这三个模型编写的应用程序的性能评估结果。我们发现，智能内存体系结构的灵活性除了具有更好的性能外，还具有其他好处。它有助于简化和优化复杂的软件运行时系统，例如Stream Virtual Machine或事务性运行时，并且可以用于特定编程模型的各种语义扩展。例如，我们在共享内存模式下实现了快速同步操作，该操作利用与数据字关联的元数据位进行细粒度锁定。

著录项

  • 作者

    Solomatnikov, Alexandre.;

  • 作者单位

    Stanford University.;

  • 授予单位 Stanford University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2009
  • 页码 167 p.
  • 总页数 167
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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