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首页> 外文学位 >Fabrication of Amorphous Indium Gallium Zinc Oxide Thin Film Transistor by using Focused Ion Beam.
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Fabrication of Amorphous Indium Gallium Zinc Oxide Thin Film Transistor by using Focused Ion Beam.

机译：利用聚焦离子束制备非晶铟镓锌氧化物薄膜晶体管。

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摘要

Compared with other transparent semiconductors, amorphous indium gallium zinc oxide (a-IGZO) has both good uniformity and high electron mobility, which make it as a good candidate for displays or large-scale transparent circuit. The goal of this research is to fabricate alpha-IGZO thin film transistor (TFT) with channel milled by focused ion beam (FIB). TFTs with different channel geometries can be achieved by applying different milling strategies, which facilitate modifying complex circuit. Technology Computer-Aided Design (TCAD) was also introduced to understand the effect of trapped charges on the device performance.;The investigation of the trapped charge at IGZO/SiO2 interface was performed on the IGZO TFT on p-Silicon substrate with thermally grown SiO2 as dielectric. The subgap density-of-state model was used for the simulation, which includes conduction band-tail trap states and donor-like state in the subgap. The result shows that the de-trapping and donor-state ionization determine the interface trapped charge density at various gate biases.;Simulation of IGZO TFT with FIB defined channel on the same substrate was also applied. The drain and source were connected intentionally during metal deposition and separated by FIB milling. Based on the simulation, the Ga ions in SiO2 introduced by the ion beam was drifted by gate bias and affects the saturation drain current.;Both side channel and direct channel transparent IGZO TFTs were fabricated on the glass substrate with coated ITO. Higher ion energy (30 keV) was used to etch through the substrate between drain and source and form side channels at the corner of milled trench. Lower ion energy (16 keV) was applied to stop the milling inside IGZO thin film and direct channel between drain and source was created. Annealing after FIB milling removed the residual Ga ions and the devices show switch feature. Direct channel shows higher saturation drain current (~10-6 A) compared with side channel (~10-7 A) because of its shorter channel length and wider width, however, it also exhibit higher gate leakage current (>10-7 A) than side channel (<10-7 A) due to larger Ga ion implantation and diffusion region in SiO2 after annealing. Hysteresis window increase and positive VON shift were also observed due to the interface trap density increase and carrier density suppression both by Ga ions.;Laser interference lithography was applied to define the IGZO active region, which gives more flexibility on TFT channel dimension and circuit modification. He-Cd laser with 325 nm wavelength was used to define 2D array of IGZO islands with period of 2.5 im. Logic gate array was designed and fabricated by combining this 2D array of IGZO islands and FIB direct channel milling. After annealing, device shows on-off feature, but high temperature (400 °C) release more free carrier and results in negative shift of VON. The row selection voltage was also introduced in the design of logic gate array to act as switch of input signals to each row separately. However, due to the long input signal sweeping time, the leakage current cannot be overlooked. The idea can be verified by AC or short pulse input signal.
机译：与其他透明半导体相比，非晶铟镓锌氧化物（a-IGZO）具有良好的均匀性和高电子迁移率，使其成为显示器或大规模透明电路的理想之选。这项研究的目标是制造具有通过聚焦离子束（FIB）研磨的沟道的α-IGZO薄膜晶体管（TFT）。可以通过应用不同的铣削策略来实现具有不同通道几何形状的TFT，这有助于修改复杂的电路。还引入了技术计算机辅助设计（TCAD），以了解捕获的电荷对器件性能的影响。；在带有热生长的SiO2的p-硅衬底上的IGZO TFT上对IGZO / SiO2界面处的捕获电荷进行了研究。作为电介质。仿真中使用了子带隙状态密度模型，该模型包括子带隙中的导带尾状陷阱态和施主态。结果表明，去俘获和施主态电离决定了在不同栅极偏压下界面俘获的电荷密度。;还对在同一基板上具有FIB定义沟道的IGZO TFT进行了仿真。在金属沉积过程中，有意将漏极和源极连接起来，并通过FIB研磨将其分开。在模拟的基础上，离子束引入的SiO2中的Ga离子由于栅极偏压而漂移，并影响饱和漏极电流。在镀有ITO的玻璃基板上分别制作了侧沟道和直接沟道透明IGZO TFT。较高的离子能量（30 keV）用于蚀刻漏极和源极之间的衬底，并在铣削沟槽的拐角处形成侧沟道。施加较低的离子能量（16 keV）以停止IGZO薄膜内部的研磨，并在漏极和源极之间建立了直接通道。 FIB铣削后的退火去除了残留的Ga离子，并且该器件具有开关功能。直接通道由于其较短的沟道长度和较宽的宽度而具有比侧通道（〜10-7 A）高的饱和漏极电流（〜10-6 A），但是，它还具有较高的栅极泄漏电流（> 10-7 A） ），因为退火后SiO2中的Ga离子注入和扩散区域更大，因此比侧通道（<10-7 A）大。由于界面陷阱密度的增加和Ga离子对载流子密度的抑制，还观察到了磁滞窗口的增加和正VON偏移。激光干涉光刻技术定义了IGZO有源区，从而为TFT沟道尺寸和电路修改提供了更大的灵活性。使用波长为325 nm的He-Cd激光定义周期为2.5 im的IGZO岛的二维阵列。通过将IGZO岛的2D阵列与FIB直接通道铣削相结合来设计和制造逻辑门阵列。退火后，器件表现出开关特性，但高温（400°C）释放出更多的自由载流子，并导致VON发生负移。在逻辑门阵列的设计中还引入了行选择电压，以分别用作输入信号到每行的切换。但是，由于较长的输入信号扫描时间，因此漏电流不能忽略。这个想法可以通过交流或短脉冲输入信号来验证。

著录项

  • 作者

    Zhu, Wencong.;

  • 作者单位

    North Carolina State University.;

  • 授予单位 North Carolina State University.;
  • 学科 Electrical engineering.;Materials science.;Nanotechnology.
  • 学位 Ph.D.
  • 年度 2015
  • 页码 189 p.
  • 总页数 189
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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