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Circuits and systems for solid-state data storage using highly scaled NAND flash memory.

机译：使用大规模NAND闪存的固态数据存储电路和系统。

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摘要

Solid-state data storage built upon NAND flash memory is fundamentally changing the memory and storage hierarchy for virtually the entire information technology infrastructure. This grand industrial trend is essentially driven by the steady bit-cost reduction of flash memory, which is enabled by continuous semiconductor technology scaling. Unfortunately, technology scaling makes flash memory devices subject to increasingly severe noise and distortion, which can largely degrade NAND flash memory storage reliability and performance. Error correction code (ECC) plays a critical role in ensuring overall system data storage integrity in presence of flash memory device reliability degradation. Conventional ECCs, such as the widely used Bose-Chaudhuri-Hocquenghem (BCH) code, have become increasingly inadequate as technology continues to scale down. Therefore, it is highly desirable to deploy a much more powerful ECC, such as low-density parity-check (LDPC) code. This thesis investigates the key design issues in practical application of LDPC code in flash-based solid-state drive (SSD).;Although LDPC code has had its success in commercial hard disk drives (HDDs), to fully exploit its error correction capability in SSDs demands unconventional fine-grained flash memory sensing, leading to an increased memory read latency. To address this important but largely unexplored issue. this thesis first investigates the impact of direct employment of soft-decision decoding LDPC codes in SSDs. Then this thesis presents three techniques to mitigate the LDPC-induced response time delay so that SSDs can fully benefit from its strong error correction capability. This thesis quantitatively evaluates these techniques by carrying out trace-based SSD simulations with runtime characterization of NAND flash memory reliability and LDPC code decoding. The study based on intensive experiments shows that these techniques used in an integrated way in SSDs can reduce the worst-case system read response time delay from over 100% down to below 20%. With the proposed techniques, a strong ECC alternative can be used in NAND flash memory to retain its reliability to respond the continuous cost reduction, and its relatively small increase of response time delay is acceptable to mainstream application users, considering a huge gain in SSD capacity, its reliability, and the price reduction.;Even in highly scaled NAND flash memory with seriously degraded reliability, the gradual wear-out and process variation of NAND flash memory makes the worst-case oriented ECC largely under-utilized most of the time. This thesis proposes to opportunistically leverage such under-utilized error correction strength to allow error-prone flash memory I/O link over-clocking, which can improve SSD speed performance. Its rationale and key design issues are thoroughly presented and studied in this thesis, and its potential effectiveness has been verified through hardware experiments and system simulations. Using sub-22nm NAND flash memory chips with I/O specs of 166MBps, extensive experiments were carried out and the results show that the proposed design strategy can enable SSDs safely operate with error-prone I/O link running at 275MBps. Trace-driven SSD simulations over a variety of workload traces show the system read response time can be reduced by over 20%. Further experiments with sub-22nm NAND flash memory chips reveal unique bit error characteristics of overclocked I/O link, based upon which this thesis develops solutions that can leverage the error characteristics to improve LDPC decoding performance. Results show that the developed techniques can reduce LDPC code decoding power consumption by 60% and reduce the decoding failure rate by over 2 orders of magnitude.
机译：建立在NAND闪存之上的固态数据存储从根本上改变了整个信息技术基础架构的存储器和存储层次结构。这种大的工业趋势基本上是由闪存的比特成本稳定下降所推动的，而闪存的不断比特成本下降是由持续的半导体技术扩展实现的。不幸的是，技术扩展使闪存设备遭受越来越严重的噪声和失真，这会大大降低NAND闪存存储的可靠性和性能。在闪存设备可靠性降低的情况下，纠错码（ECC）在确保总体系统数据存储完整性方面起着至关重要的作用。随着技术的不断缩小，诸如广泛使用的Bose-Chaudhuri-Hocquenghem（BCH）代码之类的常规ECC已变得越来越不足够。因此，非常需要部署功能更强大的ECC，例如低密度奇偶校验（LDPC）代码。本文研究了LDPC代码在基于闪存的固态驱动器（SSD）的实际应用中的关键设计问题。尽管LDPC代码已经在商用硬盘驱动器（HDD）中取得了成功，但可以充分利用其在磁盘驱动器中的纠错能力。 SSD需要非常规的细粒度闪存感测，从而增加了内存读取延迟。解决这个重要但很大程度上尚未探讨的问题。本文首先研究了直接使用软判决解码LDPC码在SSD中的影响。然后，本文提出了三种减轻LDPC引起的响应时间延迟的技术，以便SSD可以充分利用其强大的纠错能力。本文通过对基于迹线的SSD仿真进行了定量评估，这些仿真具有NAND闪存可靠性和LDPC代码解码的运行时特性。基于大量实验的研究表明，以集成方式在SSD中使用的这些技术可以将最坏情况下的系统读取响应时间延迟从100％以上降低到20％以下。利用所提出的技术，可以在NAND闪存中使用强大的ECC替代方案来保持其可靠性，以响应持续的成本降低，并且考虑到SSD容量的巨大增长，其响应时间延迟的相对较小的增长对于主流应用程序用户来说是可以接受的。 ，甚至在可靠性严重降低的大规模NAND闪存中，NAND闪存的逐渐磨损和工艺变化也使得面向最坏情况的ECC在大多数情况下都未得到充分利用。本文提出机会利用这种未充分利用的纠错强度，以使容易出错的闪存I / O链接超频，从而提高SSD的速度性能。本文对它的基本原理和关键设计问题进行了详尽的介绍和研究，并通过硬件实验和系统仿真验证了其潜在的有效性。使用I / O规格为166MBps的22nm以下NAND闪存芯片，进行了广泛的实验，结果表明，所提出的设计策略可以使SSD以275MBps的易错I / O链路安全运行。跟踪驱动的SSD在各种工作负载跟踪上的仿真表明，系统读取响应时间可以减少20％以上。低于22nm的NAND闪存芯片的进一步实验揭示了超频I / O链路的独特误码特性，在此基础上，本文提出了可以利用误码特性提高LDPC解码性能的解决方案。结果表明，所开发的技术可以将LDPC码的解码功耗降低60％，并将解码失败率降低2个数量级以上。

著录项

  • 作者

    Zhao, Kai.;

  • 作者单位

    Rensselaer Polytechnic Institute.;

  • 授予单位 Rensselaer Polytechnic Institute.;
  • 学科 Electrical engineering.;Computer science.
  • 学位 Ph.D.
  • 年度 2014
  • 页码 93 p.
  • 总页数 93
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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