The objective of this work is to unify the design methodology of the Clock Storage Elements (CSEs) and the Clock Distribution Networks (CDN) to minimize energy consumption for a given performance target. To provide an optimized circuit solution for a processor clocking system, the design space of both the CDN and CSEs need to be either modeled or explored under a range of system specifications. This work shows the methodology to achieve this design space exploration for CSEs in the context of pipeline stage critical path designs. Through the study of several mainstream CSE topologies, the novel comparative analysis provides a thorough and quantitative answer to the question: Which CSE topology is best according to my performance or energy consumption specification?;Because the answer to this question is not independent of the CDN, this work also provides a novel approach to the tuning and design of the clock distribution to minimize energy consumption. A careful balance between the CDN skew and the critical pipeline CSEs reduces overall energy consumption while maintaining the target frequency.
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