In order to improve the universality of multiplier in Galois field and to reduce the complexity of its realisation, in this paper we adopt polynomial basis algorithm to realise the operation of multiplication by circuits of simple logic gates. A reconfigurable iterative computation structure for multiplier is proposed and it can satisfy a multiplier for arbitrary binary finite field between 3 and 8 bits. The structure is also realised by using Altera' s FPGA. It is obvious that the reconfigurable multiplier in Galois field can fit the operation of multiplication in multi-standard RS code.%为了提高伽罗华有限域乘法器的通用性,降低实现的复杂度,采用自然基算法,用简单的逻辑门电路实现乘法运算过程.提出可重构的迭代计算结构,能满足域长m为3～8的乘法器,并用FPGA实现.结果表明,可重构有限域乘法器能够满足多种标准RS码的乘法运算的需要.
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