AES(Advanced Encryption Standard)是一种非常流行的对称加密算法,字节替换是AES算法中十分重要的部分.针对采用复合域方法来实现字节替换吞吐率小的问题,本文利用先计算的方法进行了5级轮内流水线设计,去除关键路径上的一些计算来降低关键路径延迟提高吞吐率.在FP-GA器件Virtex-6 XC6VLX240T上,通过Xilinx ISE 14.7进行仿真实验,结果表明在面积增加相对不大的情况下,提高了吞吐率以及吞吐率/面积比.%AES (Advanced Encryption Standard) is a very popular symmetric encryption algorithm. Byte substitution (S-Box) is an important part in AES. However, S-Box which uses the method of the composite field to implement suffers from extremely low throughput rate. In this paper , a 5-stage pipelined structure, by applying pre-computation method, some computation on the critical data path can be eliminated so as to reduce the critical path delay. The results show that the throughput rate and the ratio of data throughout and area is increased at the expense of a fairly modest increase in area.
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