In order to saving the time of add circuit and improve the efficiency,the algorithm of carry-select and margingrouping are used for the circuit generation of 32-bit adders,the cell of adder in the margin-grouping is a kind of evolved algorithm of CLA.The different margin-groups were allowed to do parallel.The result selection of higher group is determined by the adding result of lower group.This saves the waiting time of carry section.In the end,timing simulation is produced in the XILINX,final result can be obtained in the FPGA.Theoretical analyses and computer simulation verify that the method is practical,effective and easily achieved.%为了缩短加法电路运行时间,提高FPGA运行效率,利用选择进位算法和差额分组算法用硬件电路实现32位加法器,差额分组中的加法单元是利用一种改进的超前进位算法实现,选择进位算法可使不同的分组单元并行运算,利用低位的运算结果选择高位的进位为l或者进位为零的运算结果,节省了进位选择等待的时间,最后利用XILINX进行时序仿真,在FPGA上进行验证,可稳定运行在高达50兆的频率,理论分析与计算机仿真表明该算法切实可行、有效并且易于实现.
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