基于Synopsys公司3D TCAD器件模拟,该文通过改变3种工艺参数,研究65 nm体硅CMOS工艺下PMOS晶体管工艺参数变化对静态随机存储器(Static Random Access Memory,SRAM)存储单元翻转恢复效应的影响.研究结果表明:降低PMOS晶体管的P+深阱掺杂浓度、N阱掺杂浓度或调阈掺杂浓度,有助于减小翻转恢复所需的线性能量传输值(Linear Energy Transfer,LET);通过降低PMOS晶体管的P+深阱掺杂浓度和N阱掺杂浓度,使翻转恢复时间变长.该文研究结论有助于优化SRAM存储单元抗单粒子效应(Single-Event Effect,SEE)设计,并且可以指导体硅CMOS工艺下抗辐射集成电路的研究.%Based on Synopsys TCAD 3-D device simulation, the effects of PMOS transistor process parameters on the upset and recovery effect of Static Random Access Memory (SRAM) memory cell are studied in a 65-nm bulk CMOS technology, mainly by changing the three process parameters. The simulation results show that reducing the doping concentration of deep-P+-well, N-well and threshold doping concentration in PMOS transistor can decrease the Linear Energy Transfer (LET) value of the upset and recovery. By reducing the doping concentration of deep-P+-well and N-well in PMOS transistor, the time of the upset and recovery increases. The conclusion of this paper is helpful to optimize the design of Static Random Access Memory cell mitigating Single-Event Effect (SEE), and can gives a great guidance for the anti-radiation integrated circuit under bulk CMOS process.
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