提出了一种在FPGA上实现的高速全并行FIR滤波器.用窗函数设计法在MATLAB中生成滤波器抽头系数,由FIR滤波器直接型结构变换得到全并行滤波器的实现结构图,将乘法器的滤波器抽头系数固定为常数,而不是从ROM中读取.在加法器和乘法器后面都插入相应的寄存器,构成多级流水结构,用Verilog HDL在FPGA中实现128阶线性相位FIR的RTL级描述.利用网络分析仪分析了滤波器性能,实现了在单个时钟周期完成一次滤波.%A parallel high-speed pipelined FIR filter implemented in FPGA is presented. The filter tap coefficients are generated by MATLAB using windowing method. The hardware parallel structure diagram is got from linear phase direct form FIR filter structure. The filter coefficients of the multiplier is fixed as a constant, rather than read from the ROM. The inserted registers after the adders and multipliers constitute a multi-stage pipeline structure. The 128-tap linear phase FIR filter is implemented in FPGA by using verilog HDL RTL-level description. The performance of the filter is analyzed with the network analyzer machine. One point computing result is completed in single clock.
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