Design of an Error Tolerant Adder

著录项

• 来源
  《American journal of applied sciences》 |2012年第6期|p.818-824|共7页
• 作者

  Jayanthi A.N.; C.S. Ravichandran;

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• 作者单位

  Department of Electronics and Communication Engineering,Sri Ramakrishna Institute of Technology, Coimbatore, India;

  Department of Electrical and Electronics Engineering, SSK College of Engineering and Technology Coimbatore, India;

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• 收录信息
• 原文格式 PDF
• 正文语种 eng
• 中图分类
• 关键词

  error-tolerant adder (ETA); error tolerance (ET); power-delay product (PDP); minimum acceptable accuracy (MAA); least significant bit (LSB);

  机译：容错加法器（ETA）;容错（ET）;延时产品（PDP）;最低可接受精度（MAA）;最低有效位（LSB）;