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The effect of interface states, excess capacitance and series resistance in the Al/SiO2/P-Si Schottky diodes

机译:Al / SiO2 / P-Si肖特基二极管中界面状态,过大电容和串联电阻的影响

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The current-voltage (I-V) characteristics of Al/SiO2/p-Si metal-insulator-semiconductor (MIS) Schottky diodes were measured at room temperature. In addition the capacitance-voltage (C-V) and conductance-voltage (G-V) measurements are studied at frequency range of 10 kHz-1 MHz. The higher value of ideality factor of 3.25 was attributed to the presence of an interfacial insulator layer between metal and semiconductor and the high density of interface states localized at Si/SiO2 interface. The density of interface states (N-ss) distribution profile as a function of (E-ss - E-v) was extracted from the forward bias I-V measurements by taking into account the bias dependence of the effective barrier height (0,) at room temperature for the Schottky diode on the order of congruent to 4 x 10(13) eV(-1) cm(-2). These high values of N-ss were responsible for the non-ideal behaviour of I-V and C-V characteristics. Frequency dispersion in C-V and G-V can be interpreted only in terms of interface states. The Nss can follow the ac signal especially at low frequencies and yield an excess capacitance. Experimental results show that the I-V C-V and G-V characteristics of SD are affected not. only in N-ss but also in series resistance (R-s), and the location of N-ss and R-s has a significant on electrical characteristics of Schottky diodes. (c) 2005 Elsevier B.V. All rights reserved.
机译:在室温下测量Al / SiO2 / p-Si金属绝缘体半导体(MIS)肖特基二极管的电流-电压(I-V)特性。此外,还研究了在10 kHz-1 MHz频率范围内的电容电压(C-V)和电导电压(G-V)测量。理想因子的值较高,为3.25,这归因于金属和半导体之间存在界面绝缘层以及位于Si / SiO2界面处的界面态密度高。考虑到在室温下有效势垒高度(0,)的偏置依赖性,从前向偏置IV测量中提取了界面状态(N-ss)分布曲线的密度(E-ss-Ev)的函数。肖特基二极管的阶数等于4 x 10(13)eV(-1)cm(-2)。这些高的N-ss值导致了I-V和C-V特性的不理想行为。 C-V和G-V中的频率色散只能根据界面状态来解释。 Nss可以跟随交流信号,尤其是在低频时,会产生过量的电容。实验结果表明,SD的I-V C-V和G-V特性不受影响。 N-ss和R-s的位置对肖特基二极管的电特性有重要影响。 (c)2005 Elsevier B.V.保留所有权利。

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