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Reliability of High Speed Ultra Low Voltage Differential CMOS Logic

机译:高速超低压差分CMOS逻辑的可靠性

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摘要

In this paper, we present a solution to the ultra low voltage inverter by adding a keeper transistor in order to make the semi-floating-gate more stable and to reduce the current dissipation. Moreover, we also present a differential ULV inverter and elaborate on the reliability and fault tolerance of the gate. The differential ULV gate compared to both a former ULV gate and standard CMOS are given. The results are obtained through Monte-Carlo simulations.
机译:在本文中,我们提出了一种超低压逆变器解决方案,该解决方案通过添加一个保持晶体管来使半浮栅更稳定并减少电流耗散。此外,我们还介绍了一种差分ULV逆变器,并详细介绍了门的可靠性和容错能力。给出了与以前的ULV门和标准CMOS相比的差分ULV门。结果是通过蒙特卡洛模拟获得的。

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