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首页> 外文期刊>Components, Packaging and Manufacturing Technology, IEEE Transactions on >Development of Package-on-Package Using Embedded Wafer-Level Package Approach
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Development of Package-on-Package Using Embedded Wafer-Level Package Approach

机译：使用嵌入式晶圆级封装方法开发级联封装

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摘要

The ever-increasing demands of higher performance, multiple functions, higher density, and lower cost mandate the reduction of the I/O pitch on the die as well as on the package. Pitch specifications of current substrate technologies do not match the stringent fine-pitch I/O requirements. Combining embedded wafer-level package (EMWLP) and package-on-package (PoP) technologies yields a preferred solution providing fan-out area to route the fine-pitch I/Os of the chip to large-pitch I/Os on to the extra area of fan-out EMWLP packages and allows the use of conventional substrate technology. However, there are many challenges to realizing the PoP of EMWLP packages. They include the die shift during the reconstruction process, double-sided reroute distribution line (RDL), and through-mold via (TMV) connections on a thin bottom package. The assembly of EMWLP and PoP, thermal management of PoP packages, and their reliability are also major concerns. This paper describes the development of an EMWLP PoP of 12 mm $times,$12 mm footprint with 432 I/Os and the adoption of TMV to enable PoP connections. The top package circuitry is accessed through TMVs in the bottom package with double-sided RDL. Solid TMV and side-wall-plated TMV are demonstrated in the EMWLP. Mechanical modeling of the PoP is conducted to optimize the structures of the packages for good reliability performance of the PoP. Thermal dissipation of the PoP is another area of concern, because the thermal path of the top package is limited in mobile applications. The thermal performance of the developed PoP was analyzed by thermal modeling and was successfully validated by thermal characterization of the PoP module. The developed PoP successfully passed the JEDEC standard reliability tests such as moisture sensitivity level 3 test; the unbiased highly accelerated stress test for 96 h, 500 air-to-air thermal cycling (<- ex Notation="TeX">${-}{rm 40}^{circ}{rm C}$ to 125 $^{circ}{rm C}$), and 30 drop tests.
机译：对高性能，多功能，高密度和低成本的不断增长的要求，要求减小芯片和封装上的I / O间距。当前基板技术的节距规格与严格的节距I / O要求不匹配。结合嵌入式晶圆级封装（EMWLP）和级联封装（PoP）技术产生了一种首选解决方案，该解决方案提供了扇出区域，可将芯片的小间距I / O路由到大间距I / O，再到扇出EMWLP封装的面积更大，并允许使用传统的基板技术。但是，实现EMWLP软件包的PoP面临许多挑战。它们包括重建过程中的模头移位，双面重布线分配线（RDL）以及薄底封装上的直模通孔（TMV）连接。 EMWLP和PoP的组装，PoP封装的热管理及其可靠性也是主要问题。本文介绍了12毫米的EMWLP PoP的开发 $ times，$ 具有432个I / O的占地12毫米，以及采用TMV启用PoP连接。顶部封装电路可通过底部封装中带有双面RDL的TMV访问。 EMWLP演示了实心TMV和侧壁镀TMV。进行PoP的机械建模以优化包装的结构，以实现PoP的良好可靠性。 PoP的散热是另一个值得关注的领域，因为在移动应用中顶部封装的散热路径受到限制。通过热模型分析了开发的PoP的热性能，并通过PoP模块的热特性成功验证了该性能。开发的PoP成功通过了JEDEC标准可靠性测试，例如湿度敏感度3级测试；无偏高加速应力测试，持续96 h，进行500次空气-空气热循环（ <-ex Notation =“ TeX”> $ {-} {rm 40} ^ {circ} {rm C} $ 到125 $ ^ {circ} {rm C} $ ），以及30次跌落测试。

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