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首页> 外文期刊>Computational Intelligence >High-speed and area-efficient Sobel edge detector on field-programmable gate array for artificial intelligence and machine learning applications
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High-speed and area-efficient Sobel edge detector on field-programmable gate array for artificial intelligence and machine learning applications

机译：用于人工智能和机器学习应用的现场可编程门阵列上的高速和区域高效的Sobel边缘检测器

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摘要

Sobel edge detector is an algorithm commonly used in image processing and computer vision to extract edges from input images using derivative of image pixels in x and y directions against surrounding pixels. Most artificial intelligence and machine learning applications require image processing algorithms running in real time on hardware systems like field-programmable gate array (FPGAs). They typically require high throughput to match real-time speeds and since they run alongside other processing algorithms, they are required to be area efficient as well. This article proposes a high-speed and low-area implementation of the Sobel edge detection algorithm. We created the design using a novel high-level synthesis (HLS) design method based on application specific bit widths for intermediate data nodes. Register transfer level code was generated using MATLAB hardware description language (HDL) coder for HLS. The generated HDL code was implemented on Xilinx Kintex 7 field programmable gate array (FPGA) using Xilinx Vivado software. Our implementation results are superior to those obtained for similar implementations using the vendor library block sets as well as those obtained by other researchers using similar implementations in the recent past in terms of area and speed. We tested our algorithm on Kintex 7 using real-time input video with a frame resolution of 1920 x 1080. We also verified the functional simulation results with a golden MATLAB implementation using FPGA in the loop feature of HDL Verifier. In addition, we propose a generic area, speed, and power improvement methodology for different HLS tools and application designs.
机译：Sobel Edge检测器是一种常用于图像处理和计算机视觉的算法，以利用X和Y方向上的图像像素的导数来提取来自输入图像的边缘。大多数人工智能和机器学习应用程序都需要实时运行的图像处理算法，如现场可编程门阵列（FPGA）等硬件系统。它们通常需要高吞吐量以匹配实时速度，并且由于它们与其他处理算法一起运行，因此它们也需要趋于良好的区域。本文提出了Sobel边缘检测算法的高速和低区域实现。我们使用基于应用特定位宽度的中间数据节点的应用特定位宽度来创建设计。使用MATLAB硬件描述语言（HDL）编码器为HLS生成寄存器传输级别代码。使用Xilinx Vivado软件在Xilinx Kintex 7现场可编程门阵列（FPGA）上实现了所生成的HDL代码。我们的实施结果优于使用供应商库块集的类似实施的那些，以及在最近过去的过去的过去的速度下使用类似实施的其他研究人员获得的那些。我们使用具有1920 x 1080的帧分辨率的实时输入视频在Kintex 7上测试了我们的算法。我们还使用FPGA在HDL验证器的循环特征中验证了功能模拟结果，使用FPGA实现了Golden Matlab实现。此外，我们为不同的HLS工具和应用设计提出了一种通用的区域，速度和功率改进方法。

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