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Adaptive Cache Design to Enable Reliable Low-Voltage Operation

机译：自适应缓存设计可实现可靠的低压运行

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摘要

The performance/energy trade-off is widely acknowledged as a primary design consideration for modern processors. A less discussed, though equally important, trade-off is the reliability/energy trade-off. Many design features that increase reliability (e.g., redundancy, error detection, and correction) have the side effect of consuming more energy. Many energy-saving features (e.g., voltage scaling) have the side effect of making systems less reliable. In this paper, we propose an adaptive cache design that enables the operating system to optimize for performance or energy efficiency without sacrificing reliability. Our proposed mechanism enables a cache with a wide operating range, where the cache can use a variable part of its data array to store error-correcting codes. A reliable, energy-efficient cache can use up to half of its data array to store error-correcting codes so that it can reliably operate at a low voltage to reduce energy. A reliable high-performance cache uses its whole data array, but operates at a higher voltage to improve reliability while sacrificing energy. We propose a hardware mechanism that allows the operating system to choose different points within that operating range based on the desired levels of performance, energy, and reliability.
机译：性能/能耗之间的折衷被公认为现代处理器的主要设计考虑因素。尽管很少讨论，但同样重要，但还是要权衡可靠性/能量。许多提高可靠性的设计功能（例如，冗余，错误检测和纠正）具有消耗更多能量的副作用。许多节能功能（例如电压缩放）具有使系统可靠性降低的副作用。在本文中，我们提出了一种自适应缓存设计，使操作系统能够在不牺牲可靠性的情况下针对性能或能源效率进行优化。我们提出的机制可以使缓存具有较宽的操作范围，其中缓存可以使用其数据数组的可变部分来存储纠错码。可靠，节能的高速缓存最多可以使用其数据阵列的一半来存储纠错码，因此它可以在低电压下可靠地运行以减少能量。可靠的高性能缓存使用了整个数据阵列，但在更高的电压下工作以提高可靠性，同时又节省了能源。我们提出一种硬件机制，使操作系统可以根据所需的性能，能源和可靠性水平在该操作范围内选择不同的点。

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