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>Proposal of stacked type Fe-FET reconfigurable logic circuit featured with parallel processing within one silicon pillar using modified process technology of 3D NAND flash memory
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Proposal of stacked type Fe-FET reconfigurable logic circuit featured with parallel processing within one silicon pillar using modified process technology of 3D NAND flash memory
In order to realize the parallel processing within one silicon pillar, a novel stacked type Fe-FET reconfigurable logic circuit featured with parallel processing within one silicon pillar using modified process technology of 3D NAND flash memory has been newly proposed. For realizing the proposed scheme plural numbers of logics are generated within one silicon pillar. Furthermore, the outputs of these logics are connected to horizontally running wires and these wires are connected to vertically running wires which act as the output signals. For realizing this structure two improvements for fabrication scheme of 3D NAND flash memory should be introduced. First is fabrication process featured by various depth trench formation technology with one fabrication step. Second is connection technology between the output of logic block generated within the silicon pillar to horizontal running wires.
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