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首页> 外文期刊>Journal of Low Power Electronics and Applications >Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology †
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Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology †

机译：使用集成了45 nm高性能SOI-CMOS嵌入式DRAM技术的Cu TSV的三维晶圆堆叠†

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For high-volume production of 3D-stacked chips with through-silicon-vias (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology and is promising for interconnect pitches smaller than 5 µ using available tooling. Prior work has presented wafer-scale integration with tungsten TSV for low-power applications. This paper reports the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45 nm Silicon On Insulator-Complementary Metal Oxide Semiconductor (SOI-CMOS) embedded DRAM (EDRAM) having 12 to 13 copper wiring levels per strata and upto 11000 TSVs at 13 µm pitch for power and signal delivery. The wafers are thinned to 13 µm using grind polish and etch. TSVs are defined post bonding and thinning using conventional alignment techniques. Up to four additional metal levels are formed post bonding and TSV definition. A key feature of this process is its compatibility with the existing high performance POWER7™ EDRAM core requiring neither modification of the existing CMOS fabrication process nor re-design since the TSV RC characteristic is similar to typical 100–200 µm length wiring load enabling 3D macro-to-macro signaling without additional buffering Hardware measurements show no significant impact on device drive and off-current. Functional test at wafer level confirms 2.1 GHz 3D stacked EDRAM operation.
机译：对于通过硅通孔（TSV）的3D堆叠芯片的大批量生产，与凸点键合技术相比，晶圆级键合可降低生产成本，并有望通过现有工具实现小于5 µ的互连间距。先前的工作已经提出了与晶圆TSV的晶圆级集成，以用于低功耗应用。本文报道了首次使用低温氧化物键合和铜TSV来堆叠以45 nm绝缘层上的硅互补金属氧化物半导体（SOI-CMOS）嵌入式DRAM（EDRAM）制成的高性能高速缓存内核，该DRAM具有12至13条铜布线级每个层，以13 µm的间距提供多达11000个TSV，用于功率和信号传输。使用研磨抛光和蚀刻将晶圆减薄至13 µm。使用常规对准技术在键合和薄化后定义TSV。在键合和TSV定义后最多形成四个附加金属层。该工艺的关键特征是与现有高性能POWER7™EDRAM内核的兼容性，无需修改现有CMOS制造工艺，也无需重新设计，因为TSV RC特性类似于典型的100–200 µm长的接线负载，可实现3D宏到宏的信令，无需额外的缓冲硬件测量显示对设备驱动和断流没有重大影响。晶圆级功能测试证实了2.1 GHz 3D堆叠EDRAM的运行。

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