3D集成技术包括晶圆级、芯片与晶圆、芯片与芯片工艺流程,通过器件的垂直堆叠得到其性能的提升,并不依赖于基板的尺寸和技术.所有的报道均是传输速度提高,功耗降低,性能更好及更小的外形因素等优势使得这种技术的名气大振.选择晶圆或芯片级集成的决定应基于几个关键因素的考虑.对于不同种类CMOS、非CMOS器件间的集成,芯片尺寸不匹配引发了衬底的变化(如300 mm对150 mm).芯片与晶圆或芯片与芯片的堆叠也许是唯一的选择.另外,当芯片的成品率明显地不同于晶圆与晶圆键合方法时.在堆叠的晶圆中难以使确认好芯片的量达到最大.在这种情况下,应将一枚或两枚晶圆划切成小芯片并仅将合格的芯片垂直地集成.只要适当地采用晶圆与晶圆键合工艺便可实现高成品率器件同类集成.晶圆间键合具有最高的生产效率,工艺流程简便及最小的成本.满足选择晶圆级或芯片级工艺总的工艺解决方案应结合对准和键合细节来考虑决定最终的设备选择和工艺特性.所有这些工艺的论证证实对于多数产品的制造3D集成是可行的,而且有些也已成为生产的主流.%3D integration technologies include wafer level, die-to-wafer and die-to-die processing flows. The performance gains achieved by vertical stacking of devices are independent of substrates size and technology. All applications report enhanced transmission speeds, lower power consumption, better performance, and smaller form factors to name a few of the technology benefits. The decision to choose wafer or die level integration is based on several key considerations. For heterogeneous integration between CMOS and non-CMOS devices the die sizes are not matched and incoming substrate size may vary (300 mm vs. 150 mm for example). Die-to-wafer or die-to-die stacking is perhaps the only option. In addition, when the die yields are dramatically different the wafer to wafer bonding methods will not maximize the number of KGD (known good die) combinations in the stacked wafers. In these cases one or both of the wafers will be diced and only good die will be vertically integrated. Homogeneous integration of high yielding devices uses wafer to wafer technology whenever appropriate. Wafer-to-wafer bonding maximizes the throughput, simplifies the process flow, and minimizes cost. Total process solutions are tailored to the choice of wafer level or die level processing with consideration of alignment and bonding details defining the final equipment choices and process specifics. Demonstrators of all these processes have shown that 3D integration is a viable manufacturing option for many products and some are already heading to production.
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