Designing and testing robust SRAM memory for sub threshold systems is extremely challenging because of the reduced voltage margin and are highly sensitive to physical defects. Because of the unique architecture of sub-threshold cells, some of the detectable defects in case of conventional SRAM escape in sub-threshold SRAM cell. Therefore, stability fault analysis in sub-threshold SRAM cell is essential. In literature, various test methods have been demonstrated and all of them are based on voltage based test techniques. Voltage based test techniques may not be able to target all complete set of open defect faults; hence there is a need for parametric test method which supplement the existing test schemes. In this paper, transient current (IDDT) testing has been used as an alternative efficient testing method for both detection and localization of defective...........
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