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首页> 外文期刊>Electronics Letters >Two-transistor and two-magnetic-tunnel-junction multi-level cell structured spin-transfer torque magnetic random access memory with optimisations on power and reliability
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Two-transistor and two-magnetic-tunnel-junction multi-level cell structured spin-transfer torque magnetic random access memory with optimisations on power and reliability

机译：具有功率和可靠性优化的两晶体管和两个磁隧道结多级单元结构自旋转移转矩磁性随机存取存储器

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摘要

A two-transistor and two-magnetic-tunnel-junction (MTJ) multi-level cell (MLC) structure of spin-transfer torque magnetic random access memory (STT-RAM) is proposed. Compared with the conventional one-transistor and two-magnetic-tunnel-junction MLC STT-RAMs, by adding an extra access transistor and adjusting the connection of the two MTJs, the extra write power consumption on the soft bit MTJ can be reduced, which will also have a benefit to the lifetime of the soft bit. Specifically, the simulation results show that more than 75% write power consumption on the soft bit can be wiped out, and the area cost caused by the extra access transistor is negligible.
机译：提出了自旋转移矩磁随机存取存储器（STT-RAM）的两晶体管和两个磁隧道结（MTJ）多级单元（MLC）结构。与传统的单晶体管和两个磁隧道结MLC STT-RAM相比，通过添加一个额外的访问晶体管并调整两个MTJ的连接，可以减少软位MTJ上的额外写入功耗，从而减少了对软钻头的寿命也将有好处。具体而言，仿真结果表明，可以清除软位上超过75％的写功耗，并且由额外的访问晶体管引起的面积成本可以忽略不计。

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  • 来源
    《Electronics Letters》 |2016年第2期|104-105|共2页
  • 作者

    Tao Zihao; Jia Ze;

  • 作者单位

    University of Electronic Science and Technology of China, People's Republic of China;

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  • 正文语种 eng
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