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Testing and Evaluation of Silicon Die Strength

机译：硅片强度测试与评估

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In the applications of 3-D packages or stacked die packages, mostly the silicon wafers have to be ground thinner, and then the strengths of the dies from the wafers are needed for assuring good design and reliability of the packages. The purposes of this study are twofold: one is to attempt to develop a new, suitable test method for differentiating the factors that affect the variability of die strength, and the other is to investigate the failure and fatigue strengths of silicon dies. In this paper, a new test method, a plate-on-elastic-foundation test (PEFT) associated with point- or line-loading has been proposed and evaluated. It is found that the PEFT can provide not only a simple, chipping-free test for dummy or real IC chips without limitation of size, but also a (bi-axial) stress field similar to the temperature loading. The strength data of failures on IC and ground surfaces in real IC chips are presented. The good consistency of the die strength data with a minor scatter from both the point- and line-load tests is found for the specimens failed on IC surfaces, but not for the ones failed on the ground surfaces. The inconsistency of strength data from both tests for failure on ground surfaces is due to edge chipping involved. The large scatter is caused by the combined factors of the angle of grinding marks, planes of weakness of material, and loading stress states with uni-axial stress for line-load test and with unequal bi-axial stress for point-load test of rectangular specimens. The surface roughness of the dies (including the IC and ground surfaces) measured by atomic force microscopy is correlated with the failure modes and strengths from the tests. It is found that the silicon die strengths are dominated by the roughness on failure surfaces, and their failure modes always appear cracks along the directions parallel and normal to the edges of the die, which might be the weak plane of the crystal lattice of silicon. The specimens with artificial- cracks have been further tested. It has been proved that the die strength dominated by the crack initiation depends on the most severe defect but not on the amount of the defects, and its failure mode is controlled by a special weak plane after the crack initiation. Conclusively, there are four factors to influence die strength: the surface conditions of the die (including grinding-mark direction and surface roughness), the edge crack of the die (so-called chipping created during the cutting process), the weak planes of the crystal lattice of silicon, and, sometimes, different tests with various loading conditions. The fatigue strength of the die is also determined to be about 25% lower than the static one.
机译：在3-D封装或堆叠式裸片封装的应用中，大部分硅晶片必须被研磨得更薄，然后需要来自晶片的裸片的强度以确保封装的良好设计和可靠性。这项研究的目的是双重的：一个是试图开发一种新的，合适的测试方法以区分影响模具强度变异性的因素，另一个是研究硅模具的失效和疲劳强度。在本文中，提出并评估了一种新的测试方法，即与点或线荷载相关的弹性基础板测试（PEFT）。已经发现，PEFT不仅可以提供不受限制的虚拟或真实IC芯片的简单，无碎屑测试，而且还可以提供类似于温度负载的（双轴）应力场。给出了真实IC芯片中IC和接地表面故障的强度数据。对于在IC表面失败的样品，在接地表面未通过的样品，发现点强度和线负载测试的模具强度数据具有良好的一致性，并且散布的程度较小。两次测试的强度数据在地面上的破坏都是不一致的，这是由于所涉及的边缘碎裂。较大的散布是由以下因素共同引起的：磨痕的角度，材料的弱化平面以及矩形状态下的单轴向应力和矩形点负载测试的双轴应力不相等的加载应力状态标本。通过原子力显微镜测量的模具的表面粗糙度（包括IC和接地表面）与测试的失效模式和强度相关。已经发现，硅芯片的强度主要由失效表面上的粗糙度决定，并且它们的失效模式总是沿着平行于和垂直于芯片边缘的方向出现裂纹，裂纹可能是硅晶格的弱平面。带有人工裂缝的样品已经过进一步测试。已经证明，由裂纹萌生主导的模具强度取决于最严重的缺陷，而不取决于缺陷的数量，并且其破坏模式由裂纹萌生后的特殊弱平面控制。最后，有四个因素会影响模具强度：模具的表面状况（包括磨痕方向和表面粗糙度），模具的边缘裂纹（在切割过程中产生的所谓切屑），模具的弱平面硅的晶格，有时在不同的负载条件下进行不同的测试。还确定模具的疲劳强度比静态模具低约25％。

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