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首页> 外文期刊>Magnetics, IEEE Transactions on >Non-Volatile Complementary Polarizer Spin-Transfer Torque On-Chip Caches: A Device/Circuit/Systems Perspective
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Non-Volatile Complementary Polarizer Spin-Transfer Torque On-Chip Caches: A Device/Circuit/Systems Perspective

机译：非易失性互补偏振器自旋转移转矩片上缓存：从设备/电路/系统的角度看

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摘要

In this paper, we propose a new spin-transfer torque magnetic random access memory (STT-MRAM) bit-cell structure (with complementary polarizers) that is suitable for on-chip caches. Our proposed structure requires a lower average critical write current than standard STT-MRAM, with improved write-ability, readability, and reliability. A cache array based on our proposed structure is studied using a device/circuit simulation framework, which we developed for this paper. Simulation results show that at the bit-cell level, our proposed structure can achieve subnanosecond sensing delay and lower read disturb torque using a self-referenced differential READ operation. Sensing and disturb margins of our proposed cell are (1.8times ) and (2.4times ) better than standard STT-MRAM, respectively. Furthermore, near disturb-free READ operation at ≥1.5 GHz is achieved using a latch-based sense amplifier and verified in circuit simulations. In addition, content addressable memory may also be efficiently implemented using complementary polarizer spin-transfer torque (CPSTT). Transient SPICE simulations show that CPSTT may be suitable for L1 cache, with a read energy of 14 fJ/bit. System level simulation shows that a CPSTT-based L2 cache can achieve (sim 9) % lower energy consumption and >9% improvement in instructions per cycle over a standard STT-MRAM-based cache.
机译：在本文中，我们提出了一种适用于片上高速缓存的新型自旋传递扭矩磁性随机存取存储器（STT-MRAM）位单元结构（带有互补偏振器）。我们提出的结构需要比标准STT-MRAM更低的平均临界写电流，并具有提高的可写性，可读性和可靠性。我们使用为本文开发的设备/电路仿真框架研究了基于我们提出的结构的缓存阵列。仿真结果表明，在位单元级别上，我们提出的结构可以使用自参考差分读取操作实现亚纳秒级的检测延迟并降低读取干扰扭矩。我们建议的单元的感测和干扰余量为 （1.8times） 和 （2.4倍） 分别比标准STT-MRAM好。此外，使用基于锁存的读出放大器可实现≥1.5GHz的近乎无干扰的READ操作，并已在电路仿真中进行了验证。另外，还可以使用互补偏振器自旋传递转矩（CPSTT）有效地实现内容可寻址存储器。瞬态SPICE仿真表明CPSTT可能适合L1高速缓存，读取能量为14 fJ / bit。系统级仿真表明，基于CPSTT的L2缓存可以实现 （sim 9） 能耗降低％和>与基于STT-MRAM的标准缓存相比，每个周期的指令提高了9％。

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