On advance towards sub -sampling technique in phase locked loops - A review

Tonk Anu; Afzal Neelofer

首页> 外文期刊>Integration >On advance towards sub -sampling technique in phase locked loops - A review

【24h】

On advance towards sub -sampling technique in phase locked loops - A review

机译：锁相环二次采样技术的发展-综述

获取原文

获取原文并翻译 | 示例

掌桥外文数据库（机构版） >>

开具论文收录证明 >>

文献代查 >>

页面导航

摘要
著录项
相似文献
相关主题

摘要

This paper presents a symmetric review of academic and accomplished research endeavors in the field of Sub Sampling Phase Locked Loop (SSPLL) design. Adequate emphasis has been given to understand the yearn for development of Sub-Sampling PLLs. Techniques that have emerged over the recent few years in context of better FOM, Jitter and Phase Noise reduction while maintaining extraordinary circuit performance in Sub Sampling PLLs with CMOS/VLSI technology, have been captured in this paper. Consecutively, the main inspiration of this study is to present an overview of the PLL fundamentals, furtherance from analog to Digital PLL and various noises encountered in the different PLL components, important for the reader to have a better understanding about the design and analysis of Sub-Sampling PLLs.

机译：本文对子采样锁相环（SSPLL）设计领域的学术成就和研究成果进行了对称回顾。已经充分强调了对开发子采样PLL的渴望。本文介绍了近几年出现的一些技术，这些技术可以更好地降低FOM，降低抖动和降低相位噪声，同时在采用CMOS / VLSI技术的子采样PLL中保持出色的电路性能。连续地，本研究的主要目的是概述PLL的基本原理，模拟到数字PLL的优势以及在不同PLL组件中遇到的各种噪声，这对于读者更好地了解Sub的设计和分析很重要。 -采样PLL。

著录项

来源
《Integration》 |2017年第9期|90-97|共8页
作者
Tonk Anu; Afzal Neelofer;
展开▼
作者单位

Jamia Millia Islamia, Dept ECE, Engn & Technol, New Delhi, India;

Jamia Millia Islamia, Dept ECE, Engn & Technol, New Delhi, India;

展开▼
收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类
关键词
Analog PLL; Digital Phase Locked Loop (DPLL); Dead-zone; VCO; Frequency divider; Sub-Sampling PLL; Integer-N; SSPD; Figure of Merit (FOM); Fractional-N;

机译：模拟PLL;数字锁相环（DPLL）;死区;VCO;分频器;子采样PLL;整数N;SSPD;品质因数（FOM）;分数N;

相似文献

外文文献
中文文献
专利

1. Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector [J] . Gao X., Klumperink E. A. M., Socci G., Solid-State Circuits, IEEE Journal of . 2010,第9期

机译：锁相环利用次采样相位检测器的杂散抑制技术
2. A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques [J] . T. K. Kuan, S. I. Liu IEEE Journal of Solid-State Circuits . 2016,第4期

机译：使用自动环路增益控制和降低环路延迟技术的Bang Bang锁相环
3. Investigating Phase Detectors: Advances in Mature and Emerging Phase-Frequency and Time-to-Digital Detectors in Phase-Locked Looped Systems [J] . Minhad Khairun Nisa, Reaz Mamun Bin Ibne, Ali Sawal Hamid Md Microwave Magazine, IEEE . 2015,第11期

机译：研究相位检测器：锁相环系统中成熟和新兴的相频和数字时间检测器的进展
4. Phase-Control Techniques for Sub-Sampling Phase-Locked Loops [C] . Eduardo V. P. Anjos, Dominique M. M.-P. Schreurs, Guy A. E. Vandenbosch IEEE Latin American Symposium on Circuits and Systems . 2020

机译：子采样锁相环的相位控制技术
5. Low phase noise design techniques for phase locked loop based integrated RF frequency synthesizers. [D] . Kong, Weixin. 2005

机译：用于基于锁相环的集成RF频率合成器的低相位噪声设计技术。
6. Recent Advances in Microfluidic Sample Preparation and Separation Techniques for Molecular Biomarker Analysis: A Critical Review [O] . Mukul Sonker, Vishal Sahore, Adam T. Woolley -1

机译：分子生物学标志物分析的微流体样品制备和分离技术的最新进展：综述。
7. Phase-Control Techniques for Sub-Sampling Phase-Locked Loops [O] . Eduardo V. P. Anjos, Dominique M. M.-P. Schreurs, Guy A. E. Vandenbosch 2020

机译：子采样锁相环的相位控制技术

On advance towards sub -sampling technique in phase locked loops - A review

摘要

著录项

相似文献

相关主题

期刊订阅