Enhanced Degradation by Negative Bias Temperature Stress in Si Nanowire Transistor

Kensuke Ota; Masumi Saitoh; Chika Tanaka; Yukio Nakabayashi; Ken Uchida; Toshinori Numata

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Enhanced Degradation by Negative Bias Temperature Stress in Si Nanowire Transistor

机译：Si纳米线晶体管中的负偏置温度应力增强了降解

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Negative bias temperature instability in Si nanowire transistors were systematically studied. Enhanced degradation by negative bias temperature (NBT) stress in narrow nanowire transistor was observed. Nanowire width and height dependences on threshold voltage shift suggest that the larger degradation was caused by the nanowire corner effect such as electric field concentration. High speed measurements elucidated the smaller recovery ratio in nanowire transistors which is attributed to be the local charge trap at nanowire corner. Stress memorization technique does not affect the threshold voltage shift by NBT stress.

机译：系统研究了硅纳米线晶体管的负偏压温度不稳定性。观察到在窄纳米线晶体管中，负偏压（NBT）应力导致的降解增强。纳米线宽度和高度对阈值电压偏移的依赖性表明，较大的降解是由纳米线拐角效应（例如电场集中）引起的。高速测量表明，纳米线晶体管的回收率较小，这归因于纳米线角处的局部电荷陷阱。应力记忆技术不会影响NBT应力引起的阈值电压偏移。

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来源
《Japanese journal of applied physics》 |2012年第2issue2期|p.02BC08.1-02BC08.3|共3页
作者
Kensuke Ota; Masumi Saitoh; Chika Tanaka; Yukio Nakabayashi; Ken Uchida; Toshinori Numata;
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作者单位

Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, Yokohama 235-8522, Japan;

Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, Yokohama 235-8522, Japan;

Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, Yokohama 235-8522, Japan;

Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, Yokohama 235-8522, Japan;

Department of Physical Electronics, Tokyo Institute of Technology, Meguro, Tokyo 152-8552, Japan;

Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, Yokohama 235-8522, Japan;

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Enhanced Degradation by Negative Bias Temperature Stress in Si Nanowire Transistor

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