Effects of Si Layer Thickness on Solid-Phase Crystallization of Stacked Ge/Si/SiO_2 Structures

Taizoh Sadoh; Hiroki Ohta; Masanobu Miyao

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Effects of Si Layer Thickness on Solid-Phase Crystallization of Stacked Ge/Si/SiO_2 Structures

机译：Si层厚度对堆叠的Ge / Si / SiO_2结构固相结晶的影响

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The effects of amorphous-Si (a-Si) layer (thickness: 0-20nm) insertion on low-temperature (<450℃) solid-phase crystallization of a-Ge films (50 nm) were investigated. Upon the insertion of an ultrathin (<3nm) a-Si layer, incubation time increased and saturated crystallinity slightly increased. On the other hand, upon the insertion of a thick (>10nm) a-Si layer, incubation time significantly decreased and saturated crystallinity decreased. Grain sizes obtained at 425 ℃ were ～200 and ～50 nm upon the insertion of a-Si layers of 3 and 20 nm, respectively, which agrees with the results for saturated crystallinity. Moreover, upon the insertion of an intermediate-thickness (5-7 nm) a-Si layer, the nucleation rate and saturated crystallinity increased. These phenomena were explained on the basis of the Si-concentration profiles at interfaces. Thus, interface modulation is effective for realizing large-grain polycrystalline Ge.

机译：研究了非晶硅（a-Si）层（厚度：0-20nm）的插入对a-Ge膜（50nm）的低温（<450℃）固相结晶的影响。插入超薄（<3nm）的a-Si层后，孵育时间增加，饱和结晶度略有增加。另一方面，插入厚（> 10nm）的a-Si层后，孵育时间显着减少，饱和结晶度降低。插入3nm和20nm的a-Si层时，在425℃下获得的晶粒尺寸分别为〜200和〜50 nm，这与饱和结晶度的结果一致。此外，在插入中等厚度（5-7nm）的a-Si层时，成核速率和饱和结晶度增加。这些现象是根据界面处的Si浓度分布进行解释的。因此，界面调制对于实现大晶粒多晶Ge是有效的。

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《Japanese journal of applied physics》 |2009年第3issue3期|22-24|共3页
作者
Taizoh Sadoh; Hiroki Ohta; Masanobu Miyao;
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Department of Electronics, Kyushu University, Fukuoka 819-0395, Japan;

Department of Electronics, Kyushu University, Fukuoka 819-0395, Japan;

Department of Electronics, Kyushu University, Fukuoka 819-0395, Japan;

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Effects of Si Layer Thickness on Solid-Phase Crystallization of Stacked Ge/Si/SiO_2 Structures

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